[llvm-mca] Remove namespace prefixes made redundant by r345612. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345730 91177308-0d34-0410-b5e6-96231b3b80d8

Author: adibiagio

tools/llvm-mca/include/Context.h

@@ -43,13 +43,12 @@ struct PipelineOptions {
 };
 
 class Context {
-  llvm::SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
-  const llvm::MCRegisterInfo &MRI;
-  const llvm::MCSubtargetInfo &STI;
+  SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
+  const MCRegisterInfo &MRI;
+  const MCSubtargetInfo &STI;
 
 public:
-  Context(const llvm::MCRegisterInfo &R, const llvm::MCSubtargetInfo &S)
-      : MRI(R), STI(S) {}
+  Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
   Context(const Context &C) = delete;
   Context &operator=(const Context &C) = delete;
 

tools/llvm-mca/include/HWEventListener.h

@@ -62,23 +62,22 @@ class HWInstructionEvent {
 class HWInstructionIssuedEvent : public HWInstructionEvent {
 public:
   using ResourceRef = std::pair<uint64_t, uint64_t>;
-  HWInstructionIssuedEvent(
-      const InstRef &IR,
-      llvm::ArrayRef<std::pair<ResourceRef, ResourceCycles>> UR)
+  HWInstructionIssuedEvent(const InstRef &IR,
+                           ArrayRef<std::pair<ResourceRef, ResourceCycles>> UR)
       : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {}
 
-  llvm::ArrayRef<std::pair<ResourceRef, ResourceCycles>> UsedResources;
+  ArrayRef<std::pair<ResourceRef, ResourceCycles>> UsedResources;
 };
 
 class HWInstructionDispatchedEvent : public HWInstructionEvent {
 public:
-  HWInstructionDispatchedEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs,
+  HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs,
                                unsigned UOps)
       : HWInstructionEvent(HWInstructionEvent::Dispatched, IR),
         UsedPhysRegs(Regs), MicroOpcodes(UOps) {}
   // Number of physical register allocated for this instruction. There is one
   // entry per register file.
-  llvm::ArrayRef<unsigned> UsedPhysRegs;
+  ArrayRef<unsigned> UsedPhysRegs;
   // Number of micro opcodes dispatched.
   // This field is often set to the total number of micro-opcodes specified by
   // the instruction descriptor of IR.
@@ -93,12 +92,12 @@ class HWInstructionDispatchedEvent : public HWInstructionEvent {
 
 class HWInstructionRetiredEvent : public HWInstructionEvent {
 public:
-  HWInstructionRetiredEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs)
+  HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs)
       : HWInstructionEvent(HWInstructionEvent::Retired, IR),
         FreedPhysRegs(Regs) {}
   // Number of register writes that have been architecturally committed. There
   // is one entry per register file.
-  llvm::ArrayRef<unsigned> FreedPhysRegs;
+  ArrayRef<unsigned> FreedPhysRegs;
 };
 
 // A HWStallEvent represents a pipeline stall caused by the lack of hardware
@@ -142,9 +141,9 @@ class HWEventListener {
   // Events generated by the Scheduler when buffered resources are
   // consumed/freed for an instruction.
   virtual void onReservedBuffers(const InstRef &Inst,
-                                 llvm::ArrayRef<unsigned> Buffers) {}
+                                 ArrayRef<unsigned> Buffers) {}
   virtual void onReleasedBuffers(const InstRef &Inst,
-                                 llvm::ArrayRef<unsigned> Buffers) {}
+                                 ArrayRef<unsigned> Buffers) {}
 
   virtual ~HWEventListener() {}
 

tools/llvm-mca/include/HardwareUnits/LSUnit.h

@@ -129,11 +129,7 @@ class LSUnit : public HardwareUnit {
   void dump() const;
 #endif
 
-  enum Status {
-    LSU_AVAILABLE = 0,
-    LSU_LQUEUE_FULL,
-    LSU_SQUEUE_FULL
-  };
+  enum Status { LSU_AVAILABLE = 0, LSU_LQUEUE_FULL, LSU_SQUEUE_FULL };
 
   // Returns LSU_AVAILABLE if there are enough load/store queue entries to serve
   // IR. It also returns LSU_AVAILABLE if IR is not a memory operation.

tools/llvm-mca/include/HardwareUnits/RegisterFile.h

@@ -34,7 +34,7 @@ class WriteRef;
 /// Manages hardware register files, and tracks register definitions for
 /// register renaming purposes.
 class RegisterFile : public HardwareUnit {
-  const llvm::MCRegisterInfo &MRI;
+  const MCRegisterInfo &MRI;
 
   // class RegisterMappingTracker is a  physical register file (PRF) descriptor.
   // There is one RegisterMappingTracker for every PRF definition in the
@@ -85,7 +85,7 @@ class RegisterFile : public HardwareUnit {
   //
   // Users can limit the number of physical registers that are available in
   // regsiter file #0 specifying command line flag `-register-file-size=<uint>`.
-  llvm::SmallVector<RegisterMappingTracker, 4> RegisterFiles;
+  SmallVector<RegisterMappingTracker, 4> RegisterFiles;
 
   // This type is used to propagate information about the owner of a register,
   // and the cost of allocating it in the PRF. Register cost is defined as the
@@ -101,7 +101,7 @@ class RegisterFile : public HardwareUnit {
   //
   // There is a RegisterRenamingInfo object for every logical register defined
   // by the target. RegisteRenamingInfo objects are stored into vector
-  // `RegisterMappings`, and llvm::MCPhysReg IDs can be used to reference
+  // `RegisterMappings`, and MCPhysReg IDs can be used to reference
   // elements in that vector.
   //
   // Each RegisterRenamingInfo is owned by a PRF, and field `IndexPlusCost`
@@ -117,8 +117,8 @@ class RegisterFile : public HardwareUnit {
   // register definition.
   struct RegisterRenamingInfo {
     IndexPlusCostPairTy IndexPlusCost;
-    llvm::MCPhysReg RenameAs;
-    llvm::MCPhysReg AliasRegID;
+    MCPhysReg RenameAs;
+    MCPhysReg AliasRegID;
     bool AllowMoveElimination;
     RegisterRenamingInfo()
         : IndexPlusCost(std::make_pair(0U, 1U)), RenameAs(0U), AliasRegID(0U),
@@ -144,7 +144,7 @@ class RegisterFile : public HardwareUnit {
 
   // Used to track zero registers. There is one bit for each register defined by
   // the target. Bits are set for registers that are known to be zero.
-  llvm::APInt ZeroRegisters;
+  APInt ZeroRegisters;
 
   // This method creates a new register file descriptor.
   // The new register file owns all of the registers declared by register
@@ -160,41 +160,40 @@ class RegisterFile : public HardwareUnit {
   // Here FPRegisterFile contains all the registers defined by register class
   // VR128RegClass and VR256RegClass. FPRegisterFile implements 60
   // registers which can be used for register renaming purpose.
-  void addRegisterFile(const llvm::MCRegisterFileDesc &RF,
-                       llvm::ArrayRef<llvm::MCRegisterCostEntry> Entries);
+  void addRegisterFile(const MCRegisterFileDesc &RF,
+                       ArrayRef<MCRegisterCostEntry> Entries);
 
   // Consumes physical registers in each register file specified by the
   // `IndexPlusCostPairTy`. This method is called from `addRegisterMapping()`.
   void allocatePhysRegs(const RegisterRenamingInfo &Entry,
-                        llvm::MutableArrayRef<unsigned> UsedPhysRegs);
+                        MutableArrayRef<unsigned> UsedPhysRegs);
 
   // Releases previously allocated physical registers from the register file(s).
   // This method is called from `invalidateRegisterMapping()`.
   void freePhysRegs(const RegisterRenamingInfo &Entry,
-                    llvm::MutableArrayRef<unsigned> FreedPhysRegs);
+                    MutableArrayRef<unsigned> FreedPhysRegs);
 
   // Create an instance of RegisterMappingTracker for every register file
   // specified by the processor model.
   // If no register file is specified, then this method creates a default
   // register file with an unbounded number of physical registers.
-  void initialize(const llvm::MCSchedModel &SM, unsigned NumRegs);
+  void initialize(const MCSchedModel &SM, unsigned NumRegs);
 
 public:
-  RegisterFile(const llvm::MCSchedModel &SM, const llvm::MCRegisterInfo &mri,
+  RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
                unsigned NumRegs = 0);
 
   // This method updates the register mappings inserting a new register
   // definition. This method is also responsible for updating the number of
   // allocated physical registers in each register file modified by the write.
   // No physical regiser is allocated if this write is from a zero-idiom.
-  void addRegisterWrite(WriteRef Write,
-                        llvm::MutableArrayRef<unsigned> UsedPhysRegs);
+  void addRegisterWrite(WriteRef Write, MutableArrayRef<unsigned> UsedPhysRegs);
 
   // Removes write \param WS from the register mappings.
   // Physical registers may be released to reflect this update.
   // No registers are released if this write is from a zero-idiom.
   void removeRegisterWrite(const WriteState &WS,
-                           llvm::MutableArrayRef<unsigned> FreedPhysRegs);
+                           MutableArrayRef<unsigned> FreedPhysRegs);
 
   // Returns true if a move from RS to WS can be eliminated.
   // On success, it updates WriteState by setting flag `WS.isEliminated`.
@@ -212,9 +211,8 @@ class RegisterFile : public HardwareUnit {
   //
   // Current implementation can simulate up to 32 register files (including the
   // special register file at index #0).
-  unsigned isAvailable(llvm::ArrayRef<unsigned> Regs) const;
-  void collectWrites(llvm::SmallVectorImpl<WriteRef> &Writes,
-                     unsigned RegID) const;
+  unsigned isAvailable(ArrayRef<unsigned> Regs) const;
+  void collectWrites(SmallVectorImpl<WriteRef> &Writes, unsigned RegID) const;
   unsigned getNumRegisterFiles() const { return RegisterFiles.size(); }
 
   // Notify each PRF that a new cycle just started.

tools/llvm-mca/include/HardwareUnits/ResourceManager.h

@@ -189,8 +189,7 @@ class ResourceState {
   }
 
 public:
-  ResourceState(const llvm::MCProcResourceDesc &Desc, unsigned Index,
-                uint64_t Mask);
+  ResourceState(const MCProcResourceDesc &Desc, unsigned Index, uint64_t Mask);
 
   unsigned getProcResourceID() const { return ProcResourceDescIndex; }
   uint64_t getResourceMask() const { return ResourceMask; }
@@ -211,9 +210,7 @@ class ResourceState {
   /// `NumUnits` available units.
   bool isReady(unsigned NumUnits = 1) const;
 
-  bool isAResourceGroup() const {
-    return llvm::countPopulation(ResourceMask) > 1;
-  }
+  bool isAResourceGroup() const { return countPopulation(ResourceMask) > 1; }
 
   bool containsResource(uint64_t ID) const { return ResourceMask & ID; }
 
@@ -228,7 +225,7 @@ class ResourceState {
   }
 
   unsigned getNumUnits() const {
-    return isAResourceGroup() ? 1U : llvm::countPopulation(ResourceSizeMask);
+    return isAResourceGroup() ? 1U : countPopulation(ResourceSizeMask);
   }
 
   /// Checks if there is an available slot in the resource buffer.
@@ -286,10 +283,10 @@ class ResourceManager {
 
   // Keeps track of which resources are busy, and how many cycles are left
   // before those become usable again.
-  llvm::SmallDenseMap<ResourceRef, unsigned> BusyResources;
+  SmallDenseMap<ResourceRef, unsigned> BusyResources;
 
   // A table to map processor resource IDs to processor resource masks.
-  llvm::SmallVector<uint64_t, 8> ProcResID2Mask;
+  SmallVector<uint64_t, 8> ProcResID2Mask;
 
   // Returns the actual resource unit that will be used.
   ResourceRef selectPipe(uint64_t ResourceID);
@@ -305,7 +302,7 @@ class ResourceManager {
                              uint64_t ResourceMask);
 
 public:
-  ResourceManager(const llvm::MCSchedModel &SM);
+  ResourceManager(const MCSchedModel &SM);
   virtual ~ResourceManager() = default;
 
   // Overrides the selection strategy for the resource at index ResourceID in
@@ -319,17 +316,17 @@ class ResourceManager {
 
   // Returns RS_BUFFER_AVAILABLE if buffered resources are not reserved, and if
   // there are enough available slots in the buffers.
-  ResourceStateEvent canBeDispatched(llvm::ArrayRef<uint64_t> Buffers) const;
+  ResourceStateEvent canBeDispatched(ArrayRef<uint64_t> Buffers) const;
 
   // Return the processor resource identifier associated to this Mask.
   unsigned resolveResourceMask(uint64_t Mask) const;
 
   // Consume a slot in every buffered resource from array 'Buffers'. Resource
   // units that are dispatch hazards (i.e. BufferSize=0) are marked as reserved.
-  void reserveBuffers(llvm::ArrayRef<uint64_t> Buffers);
+  void reserveBuffers(ArrayRef<uint64_t> Buffers);
 
   // Release buffer entries previously allocated by method reserveBuffers.
-  void releaseBuffers(llvm::ArrayRef<uint64_t> Buffers);
+  void releaseBuffers(ArrayRef<uint64_t> Buffers);
 
   // Reserve a processor resource. A reserved resource is not available for
   // instruction issue until it is released.
@@ -346,9 +343,9 @@ class ResourceManager {
 
   void issueInstruction(
       const InstrDesc &Desc,
-      llvm::SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
+      SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
 
-  void cycleEvent(llvm::SmallVectorImpl<ResourceRef> &ResourcesFreed);
+  void cycleEvent(SmallVectorImpl<ResourceRef> &ResourcesFreed);
 
 #ifndef NDEBUG
   void dump() const {

tools/llvm-mca/include/HardwareUnits/RetireControlUnit.h

@@ -63,7 +63,7 @@ struct RetireControlUnit : public HardwareUnit {
   std::vector<RUToken> Queue;
 
 public:
-  RetireControlUnit(const llvm::MCSchedModel &SM);
+  RetireControlUnit(const MCSchedModel &SM);
 
   bool isEmpty() const { return AvailableSlots == Queue.size(); }
   bool isAvailable(unsigned Quantity = 1) const {

tools/llvm-mca/include/HardwareUnits/Scheduler.h

@@ -105,25 +105,25 @@ class Scheduler : public HardwareUnit {
   /// Issue an instruction without updating the ready queue.
   void issueInstructionImpl(
       InstRef &IR,
-      llvm::SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
+      SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
 
   // Identify instructions that have finished executing, and remove them from
   // the IssuedSet. References to executed instructions are added to input
   // vector 'Executed'.
-  void updateIssuedSet(llvm::SmallVectorImpl<InstRef> &Executed);
+  void updateIssuedSet(SmallVectorImpl<InstRef> &Executed);
 
   // Try to promote instructions from WaitSet to ReadySet.
   // Add promoted instructions to the 'Ready' vector in input.
-  void promoteToReadySet(llvm::SmallVectorImpl<InstRef> &Ready);
+  void promoteToReadySet(SmallVectorImpl<InstRef> &Ready);
 
 public:
-  Scheduler(const llvm::MCSchedModel &Model, LSUnit *Lsu)
-      : LSU(Lsu), Resources(llvm::make_unique<ResourceManager>(Model)) {
+  Scheduler(const MCSchedModel &Model, LSUnit *Lsu)
+      : LSU(Lsu), Resources(make_unique<ResourceManager>(Model)) {
     initializeStrategy(nullptr);
   }
-  Scheduler(const llvm::MCSchedModel &Model, LSUnit *Lsu,
+  Scheduler(const MCSchedModel &Model, LSUnit *Lsu,
             std::unique_ptr<SchedulerStrategy> SelectStrategy)
-      : LSU(Lsu), Resources(llvm::make_unique<ResourceManager>(Model)) {
+      : LSU(Lsu), Resources(make_unique<ResourceManager>(Model)) {
     initializeStrategy(std::move(SelectStrategy));
   }
   Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit *Lsu,
@@ -168,8 +168,8 @@ class Scheduler : public HardwareUnit {
   /// result of this event.
   void issueInstruction(
       InstRef &IR,
-      llvm::SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Used,
-      llvm::SmallVectorImpl<InstRef> &Ready);
+      SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Used,
+      SmallVectorImpl<InstRef> &Ready);
 
   /// Returns true if IR has to be issued immediately, or if IR is a zero
   /// latency instruction.
@@ -182,9 +182,9 @@ class Scheduler : public HardwareUnit {
   /// have changed in state, and that are now available to new instructions.
   /// Instructions executed are added to vector Executed, while vector Ready is
   /// populated with instructions that have become ready in this new cycle.
-  void cycleEvent(llvm::SmallVectorImpl<ResourceRef> &Freed,
-                  llvm::SmallVectorImpl<InstRef> &Ready,
-                  llvm::SmallVectorImpl<InstRef> &Executed);
+  void cycleEvent(SmallVectorImpl<ResourceRef> &Freed,
+                  SmallVectorImpl<InstRef> &Ready,
+                  SmallVectorImpl<InstRef> &Executed);
 
   /// Convert a resource mask into a valid llvm processor resource identifier.
   unsigned getResourceID(uint64_t Mask) const {
@@ -203,9 +203,9 @@ class Scheduler : public HardwareUnit {
   // This routine performs a sanity check.  This routine should only be called
   // when we know that 'IR' is not in the scheduler's instruction queues.
   void sanityCheck(const InstRef &IR) const {
-    assert(llvm::find(WaitSet, IR) == WaitSet.end());
-    assert(llvm::find(ReadySet, IR) == ReadySet.end());
-    assert(llvm::find(IssuedSet, IR) == IssuedSet.end());
+    assert(find(WaitSet, IR) == WaitSet.end() && "Already in the wait set!");
+    assert(find(ReadySet, IR) == ReadySet.end() && "Already in the ready set!");
+    assert(find(IssuedSet, IR) == IssuedSet.end() && "Already executing!");
   }
 #endif // !NDEBUG
 };