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Petar AvramovicPetar Avramovic
Petar Avramovic
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Petar Avramovic
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[MIPS GlobalISel] Fix mul operands
Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355594 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/Mips/MipsInstructionSelector.cpp

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,10 +131,23 @@ bool MipsInstructionSelector::select(MachineInstr &I,
131131
return true;
132132
}
133133

134-
if (selectImpl(I, CoverageInfo)) {
134+
if (I.getOpcode() == Mips::G_MUL) {
135+
MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
136+
.add(I.getOperand(0))
137+
.add(I.getOperand(1))
138+
.add(I.getOperand(2));
139+
if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
140+
return false;
141+
Mul->getOperand(3).setIsDead(true);
142+
Mul->getOperand(4).setIsDead(true);
143+
144+
I.eraseFromParent();
135145
return true;
136146
}
137147

148+
if (selectImpl(I, CoverageInfo))
149+
return true;
150+
138151
MachineInstr *MI = nullptr;
139152
using namespace TargetOpcode;
140153

‎test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
--- |
44

55
define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
6-
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
6+
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
77

88
...
99
---
@@ -20,7 +20,7 @@ body: |
2020
; MIPS32: liveins: $a0, $a1
2121
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
2222
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
23-
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def $hi0, implicit-def $lo0
23+
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
2424
; MIPS32: $v0 = COPY [[MUL]]
2525
; MIPS32: RetRA implicit $v0
2626
%0:gprb(s32) = COPY $a0
@@ -38,13 +38,15 @@ regBankSelected: true
3838
tracksRegLiveness: true
3939
body: |
4040
bb.1 (%ir-block.0):
41-
liveins: $a0, $a1, $a2
41+
liveins: $a0, $a1, $a2, $a3
4242
4343
; MIPS32-LABEL: name: umul_with_overflow
44-
; MIPS32: liveins: $a0, $a1, $a2
44+
; MIPS32: liveins: $a0, $a1, $a2, $a3
4545
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
4646
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
4747
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
48+
; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
49+
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
4850
; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
4951
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
5052
; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
@@ -54,18 +56,22 @@ body: |
5456
; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
5557
; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
5658
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
57-
; MIPS32: SB [[AND]], [[COPY2]], 0 :: (store 1 into %ir.pcarry_flag)
59+
; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
60+
; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
5861
; MIPS32: RetRA
5962
%0:gprb(s32) = COPY $a0
6063
%1:gprb(s32) = COPY $a1
6164
%2:gprb(p0) = COPY $a2
62-
%6:gprb(s32) = G_UMULH %0, %1
63-
%7:gprb(s32) = G_CONSTANT i32 0
64-
%8:gprb(s32) = G_ICMP intpred(ne), %6(s32), %7
65-
%9:gprb(s32) = G_CONSTANT i32 1
66-
%10:gprb(s32) = COPY %8(s32)
67-
%5:gprb(s32) = G_AND %10, %9
68-
G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
65+
%3:gprb(p0) = COPY $a3
66+
%4:gprb(s32) = G_MUL %0, %1
67+
%7:gprb(s32) = G_UMULH %0, %1
68+
%8:gprb(s32) = G_CONSTANT i32 0
69+
%9:gprb(s32) = G_ICMP intpred(ne), %7(s32), %8
70+
%10:gprb(s32) = G_CONSTANT i32 1
71+
%11:gprb(s32) = COPY %9(s32)
72+
%6:gprb(s32) = G_AND %11, %10
73+
G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
74+
G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
6975
RetRA
7076
7177
...

‎test/CodeGen/Mips/GlobalISel/legalizer/mul.mir

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
define void @mul_i16_sext() {entry: ret void}
1010
define void @mul_i16_zext() {entry: ret void}
1111
define void @mul_i16_aext() {entry: ret void}
12-
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
12+
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
1313

1414
...
1515
---
@@ -218,26 +218,31 @@ alignment: 2
218218
tracksRegLiveness: true
219219
body: |
220220
bb.1 (%ir-block.0):
221-
liveins: $a0, $a1, $a2
221+
liveins: $a0, $a1, $a2, $a3
222222
223223
; MIPS32-LABEL: name: umul_with_overflow
224-
; MIPS32: liveins: $a0, $a1, $a2
224+
; MIPS32: liveins: $a0, $a1, $a2, $a3
225225
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
226226
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
227227
; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
228+
; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
229+
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
228230
; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
229231
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
230232
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
231233
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
232-
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
233-
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
234-
; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
234+
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
235+
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
236+
; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
237+
; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into %ir.pmul)
235238
; MIPS32: RetRA
236239
%0:_(s32) = COPY $a0
237240
%1:_(s32) = COPY $a1
238241
%2:_(p0) = COPY $a2
239-
%3:_(s32), %4:_(s1) = G_UMULO %0, %1
240-
G_STORE %4(s1), %2(p0) :: (store 1 into %ir.pcarry_flag)
242+
%3:_(p0) = COPY $a3
243+
%4:_(s32), %5:_(s1) = G_UMULO %0, %1
244+
G_STORE %5(s1), %3(p0) :: (store 1 into %ir.pcarry_flag)
245+
G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
241246
RetRA
242247
243248
...

‎test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,10 @@ entry:
8888
}
8989

9090
declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
91-
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
91+
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) {
9292
; MIPS32-LABEL: umul_with_overflow:
9393
; MIPS32: # %bb.0:
94+
; MIPS32-NEXT: mul $1, $4, $5
9495
; MIPS32-NEXT: multu $4, $5
9596
; MIPS32-NEXT: mfhi $4
9697
; MIPS32-NEXT: lui $5, 0
@@ -100,11 +101,14 @@ define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
100101
; MIPS32-NEXT: lui $5, 0
101102
; MIPS32-NEXT: ori $5, $5, 1
102103
; MIPS32-NEXT: and $4, $4, $5
103-
; MIPS32-NEXT: sb $4, 0($6)
104+
; MIPS32-NEXT: sb $4, 0($7)
105+
; MIPS32-NEXT: sw $1, 0($6)
104106
; MIPS32-NEXT: jr $ra
105107
; MIPS32-NEXT: nop
106108
%res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
107109
%carry_flag = extractvalue { i32, i1 } %res, 1
110+
%mul = extractvalue { i32, i1 } %res, 0
108111
store i1 %carry_flag, i1* %pcarry_flag
112+
store i32 %mul, i32* %pmul
109113
ret void
110114
}

‎test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir

Lines changed: 19 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
--- |
44

55
define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
6-
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) { ret void }
6+
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
77

88
...
99
---
@@ -36,31 +36,37 @@ legalized: true
3636
tracksRegLiveness: true
3737
body: |
3838
bb.1 (%ir-block.0):
39-
liveins: $a0, $a1, $a2
39+
liveins: $a0, $a1, $a2, $a3
4040
4141
; MIPS32-LABEL: name: umul_with_overflow
42-
; MIPS32: liveins: $a0, $a1, $a2
42+
; MIPS32: liveins: $a0, $a1, $a2, $a3
4343
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
4444
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
4545
; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
46+
; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
47+
; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
4648
; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
4749
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
4850
; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
4951
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
50-
; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
51-
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C1]]
52-
; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into %ir.pcarry_flag)
52+
; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
53+
; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C1]]
54+
; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
55+
; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into %ir.pmul)
5356
; MIPS32: RetRA
5457
%0:_(s32) = COPY $a0
5558
%1:_(s32) = COPY $a1
5659
%2:_(p0) = COPY $a2
57-
%6:_(s32) = G_UMULH %0, %1
58-
%7:_(s32) = G_CONSTANT i32 0
59-
%8:_(s32) = G_ICMP intpred(ne), %6(s32), %7
60-
%9:_(s32) = G_CONSTANT i32 1
61-
%10:_(s32) = COPY %8(s32)
62-
%5:_(s32) = G_AND %10, %9
63-
G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
60+
%3:_(p0) = COPY $a3
61+
%4:_(s32) = G_MUL %0, %1
62+
%7:_(s32) = G_UMULH %0, %1
63+
%8:_(s32) = G_CONSTANT i32 0
64+
%9:_(s32) = G_ICMP intpred(ne), %7(s32), %8
65+
%10:_(s32) = G_CONSTANT i32 1
66+
%11:_(s32) = COPY %9(s32)
67+
%6:_(s32) = G_AND %11, %10
68+
G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
69+
G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
6470
RetRA
6571
6672
...

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