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[X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.
Remove the corresponding isel patterns that did the same thing without checking for volatile. This fixes another variation of PR42079 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364977 91177308-0d34-0410-b5e6-96231b3b80d8
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3 files changed

+27
-31
lines changed

3 files changed

+27
-31
lines changed

‎lib/Target/X86/X86ISelLowering.cpp

Lines changed: 27 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1876,6 +1876,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
18761876
setTargetDAGCombine(ISD::SIGN_EXTEND);
18771877
setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
18781878
setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
1879+
setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG);
18791880
setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG);
18801881
setTargetDAGCombine(ISD::SINT_TO_FP);
18811882
setTargetDAGCombine(ISD::UINT_TO_FP);
@@ -43914,16 +43915,35 @@ static SDValue combinePMULDQ(SDNode *N, SelectionDAG &DAG,
4391443915
}
4391543916

4391643917
static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,
43918+
TargetLowering::DAGCombinerInfo &DCI,
4391743919
const X86Subtarget &Subtarget) {
43920+
EVT VT = N->getValueType(0);
43921+
SDValue In = N->getOperand(0);
43922+
43923+
// Try to merge vector loads and extend_inreg to an extload.
43924+
if (!DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(In.getNode()) &&
43925+
In.hasOneUse()) {
43926+
auto *Ld = cast<LoadSDNode>(In);
43927+
if (!Ld->isVolatile()) {
43928+
MVT SVT = In.getSimpleValueType().getVectorElementType();
43929+
ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
43930+
EVT MemVT = EVT::getVectorVT(*DAG.getContext(), SVT,
43931+
VT.getVectorNumElements());
43932+
SDValue Load =
43933+
DAG.getExtLoad(Ext, SDLoc(N), VT, Ld->getChain(), Ld->getBasePtr(),
43934+
Ld->getPointerInfo(), MemVT, Ld->getAlignment(),
43935+
Ld->getMemOperand()->getFlags());
43936+
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
43937+
return Load;
43938+
}
43939+
}
43940+
4391843941
// Disabling for widening legalization for now. We can enable if we find a
4391943942
// case that needs it. Otherwise it can be deleted when we switch to
4392043943
// widening legalization.
4392143944
if (ExperimentalVectorWideningLegalization)
4392243945
return SDValue();
4392343946

43924-
EVT VT = N->getValueType(0);
43925-
SDValue In = N->getOperand(0);
43926-
4392743947
// Combine (ext_invec (ext_invec X)) -> (ext_invec X)
4392843948
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4392943949
if (In.getOpcode() == N->getOpcode() &&
@@ -43932,7 +43952,7 @@ static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,
4393243952

4393343953
// Attempt to combine as a shuffle.
4393443954
// TODO: SSE41 support
43935-
if (Subtarget.hasAVX()) {
43955+
if (Subtarget.hasAVX() && N->getOpcode() != ISD::SIGN_EXTEND_VECTOR_INREG) {
4393643956
SDValue Op(N, 0);
4393743957
if (TLI.isTypeLegal(VT) && TLI.isTypeLegal(In.getValueType()))
4393843958
if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
@@ -44010,7 +44030,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
4401044030
case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget);
4401144031
case ISD::SIGN_EXTEND_INREG: return combineSignExtendInReg(N, DAG, Subtarget);
4401244032
case ISD::ANY_EXTEND_VECTOR_INREG:
44013-
case ISD::ZERO_EXTEND_VECTOR_INREG: return combineExtInVec(N, DAG, Subtarget);
44033+
case ISD::SIGN_EXTEND_VECTOR_INREG:
44034+
case ISD::ZERO_EXTEND_VECTOR_INREG: return combineExtInVec(N, DAG, DCI,
44035+
Subtarget);
4401444036
case ISD::SETCC: return combineSetCC(N, DAG, Subtarget);
4401544037
case X86ISD::SETCC: return combineX86SetCC(N, DAG, Subtarget);
4401644038
case X86ISD::BRCOND: return combineBrCond(N, DAG, Subtarget);

‎lib/Target/X86/X86InstrAVX512.td

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -9632,75 +9632,55 @@ multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
96329632
(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
96339633
def : Pat<(v8i16 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
96349634
(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
9635-
def : Pat<(v8i16 (InVecOp (loadv16i8 addr:$src))),
9636-
(!cast<I>(OpcPrefix#BWZ128rm) addr:$src)>;
96379635
}
96389636
let Predicates = [HasVLX] in {
96399637
def : Pat<(v4i32 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
96409638
(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
96419639
def : Pat<(v4i32 (InVecOp (v16i8 (vzload_v4i32 addr:$src)))),
96429640
(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
9643-
def : Pat<(v4i32 (InVecOp (loadv16i8 addr:$src))),
9644-
(!cast<I>(OpcPrefix#BDZ128rm) addr:$src)>;
96459641

96469642
def : Pat<(v2i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (extloadi32i16 addr:$src)))))),
96479643
(!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
9648-
def : Pat<(v2i64 (InVecOp (loadv16i8 addr:$src))),
9649-
(!cast<I>(OpcPrefix#BQZ128rm) addr:$src)>;
96509644

96519645
def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
96529646
(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
96539647
def : Pat<(v4i32 (InVecOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
96549648
(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
96559649
def : Pat<(v4i32 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
96569650
(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
9657-
def : Pat<(v4i32 (InVecOp (loadv8i16 addr:$src))),
9658-
(!cast<I>(OpcPrefix#WDZ128rm) addr:$src)>;
96599651

96609652
def : Pat<(v2i64 (InVecOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
96619653
(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
96629654
def : Pat<(v2i64 (InVecOp (v8i16 (vzload_v4i32 addr:$src)))),
96639655
(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
9664-
def : Pat<(v2i64 (InVecOp (loadv8i16 addr:$src))),
9665-
(!cast<I>(OpcPrefix#WQZ128rm) addr:$src)>;
96669656

96679657
def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
96689658
(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
96699659
def : Pat<(v2i64 (InVecOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
96709660
(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
96719661
def : Pat<(v2i64 (InVecOp (v4i32 (vzload_v2i64 addr:$src)))),
96729662
(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
9673-
def : Pat<(v2i64 (InVecOp (loadv4i32 addr:$src))),
9674-
(!cast<I>(OpcPrefix#DQZ128rm) addr:$src)>;
96759663
}
96769664
let Predicates = [HasVLX] in {
96779665
def : Pat<(v8i32 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
96789666
(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
96799667
def : Pat<(v8i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
96809668
(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
9681-
def : Pat<(v8i32 (InVecOp (loadv16i8 addr:$src))),
9682-
(!cast<I>(OpcPrefix#BDZ256rm) addr:$src)>;
96839669

96849670
def : Pat<(v4i64 (InVecOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
96859671
(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
96869672
def : Pat<(v4i64 (InVecOp (v16i8 (vzload_v4i32 addr:$src)))),
96879673
(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
9688-
def : Pat<(v4i64 (InVecOp (loadv16i8 addr:$src))),
9689-
(!cast<I>(OpcPrefix#BQZ256rm) addr:$src)>;
96909674

96919675
def : Pat<(v4i64 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
96929676
(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
96939677
def : Pat<(v4i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
96949678
(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
9695-
def : Pat<(v4i64 (InVecOp (loadv8i16 addr:$src))),
9696-
(!cast<I>(OpcPrefix#WQZ256rm) addr:$src)>;
96979679
}
96989680
// 512-bit patterns
96999681
let Predicates = [HasAVX512] in {
97009682
def : Pat<(v8i64 (InVecOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
97019683
(!cast<I>(OpcPrefix#BQZrm) addr:$src)>;
9702-
def : Pat<(v8i64 (InVecOp (loadv16i8 addr:$src))),
9703-
(!cast<I>(OpcPrefix#BQZrm) addr:$src)>;
97049684
}
97059685
}
97069686

‎lib/Target/X86/X86InstrSSE.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4947,8 +4947,6 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy,
49474947
(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
49484948
def : Pat<(v8i32 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
49494949
(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
4950-
def : Pat<(v8i32 (InVecOp (loadv16i8 addr:$src))),
4951-
(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
49524950

49534951
def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
49544952
(!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
@@ -4957,15 +4955,11 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy,
49574955
(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
49584956
def : Pat<(v4i64 (InVecOp (v16i8 (vzload_v2i64 addr:$src)))),
49594957
(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
4960-
def : Pat<(v4i64 (InVecOp (loadv16i8 addr:$src))),
4961-
(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
49624958

49634959
def : Pat<(v4i64 (InVecOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
49644960
(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
49654961
def : Pat<(v4i64 (InVecOp (v8i16 (vzload_v2i64 addr:$src)))),
49664962
(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
4967-
def : Pat<(v4i64 (InVecOp (loadv8i16 addr:$src))),
4968-
(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
49694963
}
49704964
}
49714965

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