ARM: stop emitting blx instructions for most calls on MachO.

I'm really not sure why we were in the first place, it's the linker's job to
convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls
that could be locally resolved completely unencodable since all offsets to BLX
are multiples of 4.

rdar://26182344

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269101 91177308-0d34-0410-b5e6-96231b3b80d8

Author: TNorthover

lib/Target/ARM/ARMISelLowering.cpp

@@ -1112,7 +1112,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case ARMISD::CALL:          return "ARMISD::CALL";
   case ARMISD::CALL_PRED:     return "ARMISD::CALL_PRED";
   case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
-  case ARMISD::tCALL:         return "ARMISD::tCALL";
   case ARMISD::BRCOND:        return "ARMISD::BRCOND";
   case ARMISD::BR_JT:         return "ARMISD::BR_JT";
   case ARMISD::BR2_JT:        return "ARMISD::BR2_JT";
@@ -1909,7 +1908,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
     if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
       CallOpc = ARMISD::CALL_NOLINK;
     else
-      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
+      CallOpc = ARMISD::CALL;
   } else {
     if (!isDirect && !Subtarget->hasV5TOps())
       CallOpc = ARMISD::CALL_NOLINK;

lib/Target/ARM/ARMISelLowering.h

@@ -43,7 +43,6 @@ namespace llvm {
       CALL,         // Function call.
       CALL_PRED,    // Function call that's predicable.
       CALL_NOLINK,  // Function call with branch not branch-and-link.
-      tCALL,        // Thumb function call.
       BRCOND,       // Conditional branch.
       BR_JT,        // Jumptable branch.
       BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).

lib/Target/ARM/ARMInstrThumb.td

@@ -15,10 +15,6 @@
 // Thumb specific DAG Nodes.
 //
 
-def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
-                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
-                       SDNPVariadic]>;
-
 def imm_sr_XFORM: SDNodeXForm<imm, [{
   unsigned Imm = N->getZExtValue();
   return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
@@ -460,7 +456,7 @@ let isCall = 1,
   def tBL  : TIx2<0b11110, 0b11, 1,
                   (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
                   "bl${p}\t$func",
-                  [(ARMtcall tglobaladdr:$func)]>,
+                  [(ARMcall tglobaladdr:$func)]>,
              Requires<[IsThumb]>, Sched<[WriteBrL]> {
     bits<24> func;
     let Inst{26} = func{23};
@@ -473,8 +469,7 @@ let isCall = 1,
   // ARMv5T and above, also used for Thumb2
   def tBLXi : TIx2<0b11110, 0b11, 0,
                  (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
-                   "blx${p}\t$func",
-                   [(ARMcall tglobaladdr:$func)]>,
+                   "blx${p}\t$func", []>,
               Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
     bits<24> func;
     let Inst{26} = func{23};
@@ -488,7 +483,7 @@ let isCall = 1,
   // Also used for Thumb2
   def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
                   "blx${p}\t$func",
-                  [(ARMtcall GPR:$func)]>,
+                  [(ARMcall GPR:$func)]>,
               Requires<[IsThumb, HasV5T]>,
               T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
     bits<4> func;
@@ -1380,11 +1375,9 @@ def : T1Pat<(ARMWrapperJT tjumptable:$dst),
             (tLEApcrelJT tjumptable:$dst)>;
 
 // Direct calls
-def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
+def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>,
       Requires<[IsThumb]>;
 
-def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
-      Requires<[IsThumb, HasV5T, IsNotMClass]>;
 
 // Indirect calls to ARM routines
 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,

test/CodeGen/ARM/2010-11-29-PrologueBug.ll

@@ -1,24 +1,17 @@
-; RUN: llc < %s -mtriple=armv7-apple-ios   | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB2
+; RUN: llc < %s -mtriple=armv7-apple-ios   | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
 ; rdar://8690640
 
 define i32* @t(i32* %x) nounwind {
 entry:
-; ARM-LABEL: t:
-; ARM: push
-; ARM: mov r7, sp
-; ARM: bl _foo
-; ARM: bl _foo
-; ARM: bl _foo
-; ARM: pop {r7, pc}
+; CHECK-LABEL: t:
+; CHECK: push
+; CHECK: mov r7, sp
+; CHECK: bl _foo
+; CHECK: bl _foo
+; CHECK: bl _foo
+; CHECK: pop {r7, pc}
 
-; THUMB2-LABEL: t:
-; THUMB2: push
-; THUMB2: mov r7, sp
-; THUMB2: blx _foo
-; THUMB2: blx _foo
-; THUMB2: blx _foo
-; THUMB2: pop
   %0 = tail call i32* @foo(i32* %x) nounwind
   %1 = tail call i32* @foo(i32* %0) nounwind
   %2 = tail call i32* @foo(i32* %1) nounwind

test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll

@@ -3,7 +3,7 @@
 ; CHECK: _f
 ; CHECK-NOT: ands
 ; CHECK: cmp
-; CHECK: blxle _g
+; CHECK: blle _g
 
 define i32 @f(i32 %a, i32 %b) nounwind ssp {
 entry:

test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll

@@ -3,7 +3,7 @@
 ; CHECK: _f
 ; CHECK: adds
 ; CHECK-NOT: cmp
-; CHECK: blxeq _h
+; CHECK: bleq _h
 
 define i32 @f(i32 %a, i32 %b) nounwind ssp {
 entry:
@@ -22,7 +22,7 @@ if.end:                                           ; preds = %if.then, %entry
 ; CHECK: _g
 ; CHECK: orrs
 ; CHECK-NOT: cmp
-; CHECK: blxeq _h
+; CHECK: bleq _h
 
 define i32 @g(i32 %a, i32 %b) nounwind ssp {
 entry:

test/CodeGen/ARM/2011-04-26-SchedTweak.ll

@@ -38,9 +38,9 @@ bb:
 bb1:
 ; CHECK: %bb1
 ; CHECK-NOT: umull
-; CHECK: blx _Get
+; CHECK: bl _Get
 ; CHECK: umull
-; CHECK: blx _foo
+; CHECK: bl _foo
   %tmp5 = load i32, i32* %block_size, align 4
   %tmp6 = load i32, i32* %block_count, align 4
   %tmp7 = call %struct.FF* @Get() nounwind

test/CodeGen/ARM/2011-06-09-TailCallByVal.ll

@@ -29,7 +29,7 @@ target triple = "thumbv7-apple-darwin10"
 @"\01_fnmatch.initial" = external constant %union.__mbstate_t, align 4
 
 ; CHECK: _fnmatch
-; CHECK: blx _fnmatch1
+; CHECK: bl _fnmatch1
 
 define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize {
 entry: