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lines changed Original file line number Diff line number Diff line change 3
3
-DAPPLICATION_ADDR=0x8040000
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4
-DAPPLICATION_RAM_ADDR=0x24000000
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5
-DAPPLICATION_RAM_SIZE=0x80000
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- -DAPPLICATION_SIZE=0xc0000
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+ -DAPPLICATION_SIZE=0x1c0000
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7
-DMBED_RAM1_SIZE=0x80000
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8
-DMBED_RAM1_START=0x24000000
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9
-DMBED_RAM_SIZE=0x80000
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-DMBED_RAM_START=0x24000000
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- -DMBED_ROM_SIZE=0x100000
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+ -DMBED_ROM_SIZE=0x200000
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-DMBED_ROM_START=0x8000000
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-DMBED_TRAP_ERRORS_ENABLED=1
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-Os
Original file line number Diff line number Diff line change 5
5
-DAPPLICATION_ADDR=0x8040000
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-DAPPLICATION_RAM_ADDR=0x24000000
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7
-DAPPLICATION_RAM_SIZE=0x80000
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- -DAPPLICATION_SIZE=0xc0000
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+ -DAPPLICATION_SIZE=0x1c0000
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-DMBED_RAM1_SIZE=0x80000
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10
-DMBED_RAM1_START=0x24000000
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-DMBED_RAM_SIZE=0x80000
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-DMBED_RAM_START=0x24000000
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- -DMBED_ROM_SIZE=0x100000
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+ -DMBED_ROM_SIZE=0x200000
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-DMBED_ROM_START=0x8000000
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-DMBED_TRAP_ERRORS_ENABLED=1
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-Os
Original file line number Diff line number Diff line change 44
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-DEXTRA_IDLE_STACK_REQUIRED
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-DFEATURE_BLE=1
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-D__FPU_PRESENT=1
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+ -DLSE_STARTUP_TIMEOUT=200
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-D__MBED__=1
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- -DMBED_BUILD_TIMESTAMP=1657634193.764244
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+ -DMBED_BUILD_TIMESTAMP=1661346223.3493464
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-D__MBED_CMSIS_RTOS_CM
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-DMBED_TICKLESS
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-DMBEDTLS_FS_IO
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-DUSE_HAL_DRIVER
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-DVIRTIO_MASTER_ONLY
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-DMBED_NO_GLOBAL_USING_DIRECTIVE=1
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- -DCORE_MAJOR=3
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- -DCORE_MINOR=2
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- -DCORE_PATCH=0
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+ -DCORE_MAJOR=
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+ -DCORE_MINOR=
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+ -DCORE_PATCH=
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-DUSE_ARDUINO_PINOUT
Original file line number Diff line number Diff line change 1
- -DMBED_APP_SIZE=0xc0000
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+ -DMBED_APP_SIZE=0x1c0000
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2
-DMBED_APP_START=0x8040000
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3
-DMBED_BOOT_STACK_SIZE=1024
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-DMBED_RAM1_SIZE=0x80000
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5
-DMBED_RAM1_START=0x24000000
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6
-DMBED_RAM_SIZE=0x80000
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-DMBED_RAM_START=0x24000000
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- -DMBED_ROM_SIZE=0x100000
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+ -DMBED_ROM_SIZE=0x200000
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-DMBED_ROM_START=0x8000000
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-DXIP_ENABLE=0
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-Wl,--gc-sections
Original file line number Diff line number Diff line change 1
1
MEMORY
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2
{
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- FLASH (rx) : ORIGIN = 0x8040000, LENGTH = CM4_BINARY_START - 0x8040000
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+ FLASH (rx) : ORIGIN = 0x8040000, LENGTH = 0x1c0000
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4
DTCMRAM (rwx) : ORIGIN = 0x20000000 + (((166 * 4) + 7) & 0xFFFFFFF8), LENGTH = 128K - (((166 * 4) + 7) & 0xFFFFFFF8)
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RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 0x80000
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RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
Original file line number Diff line number Diff line change 382
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#define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:MCU_STM32H7
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#define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32
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#define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1|USE_LPUART_CLK_PCLK3 // set by target:MCU_STM32
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- #define MBED_CONF_TARGET_LSE_AVAILABLE 0 // set by target:PORTENTA_H7
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+ #define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:PORTENTA_H7
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#define MBED_CONF_TARGET_LSE_BYPASS 1 // set by target:PORTENTA_H7
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#define MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL RCC_LSEDRIVE_LOW // set by target:MCU_STM32H7
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#define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target
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