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Automerge: Revert "[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#122741)"
This reverts commit f12078e. Breaks `check-llvm`, see comments on llvm/llvm-project#122741
2 parents 4526ddf + e18a77c commit e7dba86

11 files changed

+77
-60
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6282,10 +6282,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
62826282
Flags.setNonNeg(N1->getFlags().hasNonNeg());
62836283
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
62846284
}
6285-
6286-
if (OpOpcode == ISD::POISON)
6287-
return getPOISON(VT);
6288-
62896285
if (N1.isUndef())
62906286
// sext(undef) = 0, because the top bits will all be the same.
62916287
return getConstant(0, DL, VT);
@@ -6306,10 +6302,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63066302
Flags.setNonNeg(N1->getFlags().hasNonNeg());
63076303
return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
63086304
}
6309-
6310-
if (OpOpcode == ISD::POISON)
6311-
return getPOISON(VT);
6312-
63136305
if (N1.isUndef())
63146306
// zext(undef) = 0, because the top bits will be zero.
63156307
return getConstant(0, DL, VT);

‎llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1019,7 +1019,7 @@ define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
10191019
define void @sameOperandBFI(i64 %src, i64 %src2, ptr %ptr) {
10201020
; LLC-LABEL: sameOperandBFI:
10211021
; LLC: // %bb.0: // %entry
1022-
; LLC-NEXT: cbnz w8, .LBB30_2
1022+
; LLC-NEXT: cbnz wzr, .LBB30_2
10231023
; LLC-NEXT: // %bb.1: // %if.else
10241024
; LLC-NEXT: lsr x8, x0, #47
10251025
; LLC-NEXT: and w9, w1, #0x3

‎llvm/test/CodeGen/AArch64/optimize-cond-branch.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ define void @func() uwtable {
1616
; CHECK-NEXT: mov w8, #1 // =0x1
1717
; CHECK-NEXT: cbnz w8, .LBB0_3
1818
; CHECK-NEXT: // %bb.1: // %b1
19-
; CHECK-NEXT: cbz w8, .LBB0_4
19+
; CHECK-NEXT: cbz wzr, .LBB0_4
2020
; CHECK-NEXT: // %bb.2: // %b3
2121
; CHECK-NEXT: ldr w8, [x8]
2222
; CHECK-NEXT: and w0, w8, #0x100

‎llvm/test/CodeGen/AArch64/sve-extract-element.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -523,6 +523,7 @@ define double @test_lanex_2xf64(<vscale x 2 x double> %a, i32 %x) #0 {
523523
define i32 @test_undef_lane_4xi32(<vscale x 4 x i32> %a) #0 {
524524
; CHECK-LABEL: test_undef_lane_4xi32:
525525
; CHECK: // %bb.0:
526+
; CHECK-NEXT: fmov w0, s0
526527
; CHECK-NEXT: ret
527528
%b = extractelement <vscale x 4 x i32> %a, i32 poison
528529
ret i32 %b

‎llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -92,17 +92,27 @@ define i16 @bitcast_f16_to_i16(half %a, i32 %b) {
9292
; GCN-LABEL: bitcast_f16_to_i16:
9393
; GCN: ; %bb.0:
9494
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
95+
; GCN-NEXT: v_mov_b32_e32 v2, v0
96+
; GCN-NEXT: v_mov_b32_e32 v0, 0
9597
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
96-
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
98+
; GCN-NEXT: v_cvt_f16_f32_e32 v1, v2
9799
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
98100
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
101+
; GCN-NEXT: s_cbranch_execnz .LBB1_3
102+
; GCN-NEXT: ; %bb.1: ; %Flow
103+
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
104+
; GCN-NEXT: s_cbranch_execnz .LBB1_4
105+
; GCN-NEXT: .LBB1_2: ; %end
106+
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
107+
; GCN-NEXT: s_setpc_b64 s[30:31]
108+
; GCN-NEXT: .LBB1_3: ; %cmp.false
109+
; GCN-NEXT: v_mov_b32_e32 v0, v1
99110
; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
100111
; GCN-NEXT: s_cbranch_execz .LBB1_2
101-
; GCN-NEXT: ; %bb.1:
102-
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
112+
; GCN-NEXT: .LBB1_4: ; %cmp.true
113+
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v1
103114
; GCN-NEXT: v_add_f32_e32 v0, 0x38000000, v0
104115
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
105-
; GCN-NEXT: .LBB1_2:
106116
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
107117
; GCN-NEXT: s_setpc_b64 s[30:31]
108118
;
@@ -239,9 +249,10 @@ define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) {
239249
; GCN-LABEL: bitcast_bf16_to_i16:
240250
; GCN: ; %bb.0:
241251
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
252+
; GCN-NEXT: v_mov_b32_e32 v2, v0
253+
; GCN-NEXT: v_mov_b32_e32 v0, 0
242254
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
243-
; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v0
244-
; GCN-NEXT: ; implicit-def: $vgpr0
255+
; GCN-NEXT: v_mul_f32_e32 v1, 1.0, v2
245256
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
246257
; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
247258
; GCN-NEXT: s_cbranch_execnz .LBB3_3

‎llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8383,10 +8383,10 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
83838383
; GFX7LESS: ; %bb.0:
83848384
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
83858385
; GFX7LESS-NEXT: s_load_dword s6, s[4:5], 0xd
8386-
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
8387-
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0
8388-
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
8389-
; GFX7LESS-NEXT: ; implicit-def: $vgpr0
8386+
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 0
8387+
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v1, exec_lo, 0
8388+
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v1, exec_hi, v1
8389+
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
83908390
; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc
83918391
; GFX7LESS-NEXT: s_cbranch_execz .LBB15_2
83928392
; GFX7LESS-NEXT: ; %bb.1:
@@ -8731,10 +8731,10 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
87318731
; GFX7LESS-NEXT: s_mov_b64 s[6:7], exec
87328732
; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
87338733
; GFX7LESS-NEXT: s_load_dword s10, s[4:5], 0xd
8734-
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
8735-
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v4, s7, v0
8734+
; GFX7LESS-NEXT: v_mov_b32_e32 v0, 0
8735+
; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s6, 0
8736+
; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v4, s7, v1
87368737
; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
8737-
; GFX7LESS-NEXT: ; implicit-def: $vgpr0
87388738
; GFX7LESS-NEXT: s_and_saveexec_b64 s[8:9], vcc
87398739
; GFX7LESS-NEXT: s_cbranch_execz .LBB16_4
87408740
; GFX7LESS-NEXT: ; %bb.1:

‎llvm/test/CodeGen/AMDGPU/ctpop16.ll

Lines changed: 21 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1292,7 +1292,7 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
12921292
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
12931293
; SI-NEXT: s_endpgm
12941294
; SI-NEXT: .LBB14_4:
1295-
; SI-NEXT: ; implicit-def: $vgpr0
1295+
; SI-NEXT: v_mov_b32_e32 v0, 0
12961296
; SI-NEXT: s_branch .LBB14_2
12971297
;
12981298
; VI-LABEL: ctpop_i16_in_br:
@@ -1329,47 +1329,48 @@ define amdgpu_kernel void @ctpop_i16_in_br(ptr addrspace(1) %out, ptr addrspace(
13291329
; EG: ; %bb.0: ; %entry
13301330
; EG-NEXT: ALU 0, @20, KC0[], KC1[]
13311331
; EG-NEXT: TEX 0 @14
1332-
; EG-NEXT: ALU_PUSH_BEFORE 3, @21, KC0[], KC1[]
1332+
; EG-NEXT: ALU_PUSH_BEFORE 4, @21, KC0[], KC1[]
13331333
; EG-NEXT: JUMP @7 POP:1
1334-
; EG-NEXT: ALU 0, @25, KC0[CB0:0-32], KC1[]
1334+
; EG-NEXT: ALU 0, @26, KC0[CB0:0-32], KC1[]
13351335
; EG-NEXT: TEX 0 @16
1336-
; EG-NEXT: ALU_POP_AFTER 1, @26, KC0[], KC1[]
1337-
; EG-NEXT: ALU_PUSH_BEFORE 2, @28, KC0[CB0:0-32], KC1[]
1336+
; EG-NEXT: ALU_POP_AFTER 1, @27, KC0[], KC1[]
1337+
; EG-NEXT: ALU_PUSH_BEFORE 2, @29, KC0[CB0:0-32], KC1[]
13381338
; EG-NEXT: JUMP @11 POP:1
13391339
; EG-NEXT: TEX 0 @18
1340-
; EG-NEXT: ALU_POP_AFTER 0, @31, KC0[], KC1[]
1341-
; EG-NEXT: ALU 11, @32, KC0[], KC1[]
1340+
; EG-NEXT: ALU_POP_AFTER 0, @32, KC0[], KC1[]
1341+
; EG-NEXT: ALU 11, @33, KC0[], KC1[]
13421342
; EG-NEXT: MEM_RAT MSKOR T1.XW, T0.X
13431343
; EG-NEXT: CF_END
13441344
; EG-NEXT: Fetch clause starting at 14:
1345-
; EG-NEXT: VTX_READ_16 T1.X, T0.X, 46, #3
1345+
; EG-NEXT: VTX_READ_16 T2.X, T1.X, 46, #3
13461346
; EG-NEXT: Fetch clause starting at 16:
1347-
; EG-NEXT: VTX_READ_16 T1.X, T1.X, 2, #1
1347+
; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #1
13481348
; EG-NEXT: Fetch clause starting at 18:
1349-
; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3
1349+
; EG-NEXT: VTX_READ_16 T0.X, T1.X, 44, #3
13501350
; EG-NEXT: ALU clause starting at 20:
1351-
; EG-NEXT: MOV * T0.X, 0.0,
1351+
; EG-NEXT: MOV * T1.X, 0.0,
13521352
; EG-NEXT: ALU clause starting at 21:
1353-
; EG-NEXT: MOV T1.W, literal.x,
1354-
; EG-NEXT: SETNE_INT * T0.W, T1.X, 0.0,
1355-
; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)
1353+
; EG-NEXT: MOV T0.X, literal.x,
1354+
; EG-NEXT: MOV T1.W, literal.y,
1355+
; EG-NEXT: SETNE_INT * T0.W, T2.X, 0.0,
1356+
; EG-NEXT: 0(0.000000e+00), 1(1.401298e-45)
13561357
; EG-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,
1357-
; EG-NEXT: ALU clause starting at 25:
1358-
; EG-NEXT: MOV * T1.X, KC0[2].Z,
13591358
; EG-NEXT: ALU clause starting at 26:
1359+
; EG-NEXT: MOV * T0.X, KC0[2].Z,
1360+
; EG-NEXT: ALU clause starting at 27:
13601361
; EG-NEXT: MOV * T1.W, literal.x,
13611362
; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
1362-
; EG-NEXT: ALU clause starting at 28:
1363+
; EG-NEXT: ALU clause starting at 29:
13631364
; EG-NEXT: MOV T0.W, KC0[2].Y,
13641365
; EG-NEXT: SETE_INT * T1.W, T1.W, 0.0,
13651366
; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,
1366-
; EG-NEXT: ALU clause starting at 31:
1367-
; EG-NEXT: BCNT_INT * T1.X, T0.X,
13681367
; EG-NEXT: ALU clause starting at 32:
1368+
; EG-NEXT: BCNT_INT * T0.X, T0.X,
1369+
; EG-NEXT: ALU clause starting at 33:
13691370
; EG-NEXT: LSHL * T1.W, T0.W, literal.x,
13701371
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
13711372
; EG-NEXT: AND_INT T1.W, PV.W, literal.x,
1372-
; EG-NEXT: AND_INT * T2.W, T1.X, literal.y,
1373+
; EG-NEXT: AND_INT * T2.W, T0.X, literal.y,
13731374
; EG-NEXT: 24(3.363116e-44), 65535(9.183409e-41)
13741375
; EG-NEXT: LSHL T1.X, PS, PV.W,
13751376
; EG-NEXT: LSHL * T1.W, literal.x, PV.W,

‎llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,16 +6,15 @@
66
define amdgpu_kernel void @foo() {
77
; CHECK-LABEL: foo:
88
; CHECK: ; %bb.0: ; %entry
9-
; CHECK-NEXT: ; %bb.1: ; %LeafBlock1
10-
; CHECK-NEXT: s_cmp_eq_u32 s0, 10
11-
; CHECK-NEXT: s_cbranch_scc1 .LBB0_3
12-
; CHECK-NEXT: ; %bb.2:
9+
; CHECK-NEXT: s_cbranch_execnz .LBB0_2
10+
; CHECK-NEXT: ; %bb.1: ; %LeafBlock1
11+
; CHECK-NEXT: .LBB0_2: ; %foo.exit
1312
; CHECK-NEXT: s_mov_b32 s3, 0xf000
1413
; CHECK-NEXT: s_mov_b32 s2, -1
1514
; CHECK-NEXT: v_mov_b32_e32 v0, 0
1615
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0
1716
; CHECK-NEXT: s_endpgm
18-
; CHECK-NEXT: .LBB0_3:
17+
; CHECK-NEXT: ; %bb.3: ; %sw.bb10
1918
entry:
2019
switch i8 poison, label %foo.exit [
2120
i8 4, label %sw.bb4

‎llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,13 +29,17 @@ define protected amdgpu_kernel void @_RSENC_PRInit______________________________
2929
; CHECK-NEXT: s_cmp_eq_u32 s4, 0
3030
; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
3131
; CHECK-NEXT: ; %bb.3: ; %if.end60
32+
; CHECK-NEXT: s_mov_b64 vcc, exec
3233
; CHECK-NEXT: s_cbranch_execz .LBB0_11
3334
; CHECK-NEXT: ; %bb.4: ; %if.end5.i
34-
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
35+
; CHECK-NEXT: s_mov_b64 vcc, vcc
36+
; CHECK-NEXT: s_cbranch_vccz .LBB0_11
3537
; CHECK-NEXT: ; %bb.5: ; %if.end5.i314
36-
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
38+
; CHECK-NEXT: s_mov_b64 vcc, exec
39+
; CHECK-NEXT: s_cbranch_execz .LBB0_11
3740
; CHECK-NEXT: ; %bb.6: ; %if.end5.i338
38-
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
41+
; CHECK-NEXT: s_mov_b64 vcc, vcc
42+
; CHECK-NEXT: s_cbranch_vccz .LBB0_11
3943
; CHECK-NEXT: ; %bb.7: ; %if.end5.i362
4044
; CHECK-NEXT: v_mov_b32_e32 v0, 0
4145
; CHECK-NEXT: s_getpc_b64 s[4:5]
@@ -46,7 +50,7 @@ define protected amdgpu_kernel void @_RSENC_PRInit______________________________
4650
; CHECK-NEXT: buffer_store_byte v0, v0, s[0:3], 0 offen
4751
; CHECK-NEXT: s_waitcnt vmcnt(1)
4852
; CHECK-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:257
49-
; CHECK-NEXT: s_cbranch_scc0 .LBB0_11
53+
; CHECK-NEXT: s_cbranch_execz .LBB0_11
5054
; CHECK-NEXT: ; %bb.8: ; %if.end5.i400
5155
; CHECK-NEXT: flat_load_ubyte v0, v[0:1]
5256
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)

‎llvm/test/CodeGen/PowerPC/undef-args.ll

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,5 @@
1-
;; Tests that extending poison results in poison.
2-
;; Also tests that there are no redundant instructions loading 0 into argument registers for unused arguments.
3-
4-
; REQUIRES: asserts
1+
;; Tests that extending poison results in undef.
2+
;; Also tests that there are redundant instructions loading 0 into argument registers for unused arguments.
53

64
; REQUIRES: asserts
75

@@ -64,7 +62,7 @@ entry:
6462
; CHECKISEL64-NEXT: t7: i64 = Register $x1
6563
; CHECKISEL64-NEXT: t0: ch,glue = EntryToken
6664
; CHECKISEL64-NEXT: t6: ch,glue = callseq_start t0, TargetConstant:i64<112>, TargetConstant:i64<0>
67-
; CHECKISEL64-NEXT: t11: ch,glue = CopyToReg t6, Register:i64 $x3, poison:i64
65+
; CHECKISEL64-NEXT: t11: ch,glue = CopyToReg t6, Register:i64 $x3, Constant:i64<0>
6866
; CHECKISEL64-NEXT: t13: ch,glue = CopyToReg t11, Register:i64 $x4, Constant:i64<255>, t11:1
6967
; CHECKISEL64-NEXT: t17: ch,glue = PPCISD::CALL_NOP t13, MCSymbol:i64, Register:i64 $x3, Register:i64 $x4, Register:i64 $x2, RegisterMask:Untyped, t13:1
7068
; CHECKISEL64-NEXT: t18: ch,glue = callseq_end t17, TargetConstant:i64<112>, TargetConstant:i64<0>, t17:1
@@ -74,6 +72,7 @@ entry:
7472
; CHECKASM64-NEXT: # %bb.0: # %entry
7573
; CHECKASM64-NEXT: mflr 0
7674
; CHECKASM64-NEXT: stdu 1, -112(1)
75+
; CHECKASM64-NEXT: li 3, 0
7776
; CHECKASM64-NEXT: li 4, 255
7877
; CHECKASM64-NEXT: std 0, 128(1)
7978
; CHECKASM64-NEXT: bl .bar32
@@ -105,7 +104,7 @@ entry:
105104
; CHECKISEL32-NEXT: t9: i32 = Register $r1
106105
; CHECKISEL32-NEXT: t0: ch,glue = EntryToken
107106
; CHECKISEL32-NEXT: t8: ch,glue = callseq_start t0, TargetConstant:i32<56>, TargetConstant:i32<0>
108-
; CHECKISEL32-NEXT: t11: ch,glue = CopyToReg t8, Register:i32 $r3, poison:i32
107+
; CHECKISEL32-NEXT: t11: ch,glue = CopyToReg t8, Register:i32 $r3, Constant:i32<0>
109108
; CHECKISEL32-NEXT: t13: ch,glue = CopyToReg t11, Register:i32 $r4, Constant:i32<255>, t11:1
110109
; CHECKISEL32-NEXT: t17: ch,glue = PPCISD::CALL_NOP t13, MCSymbol:i32, Register:i32 $r3, Register:i32 $r4, Register:i32 $r2, RegisterMask:Untyped, t13:1
111110
; CHECKISEL32-NEXT: t18: ch,glue = callseq_end t17, TargetConstant:i32<56>, TargetConstant:i32<0>, t17:1
@@ -115,6 +114,7 @@ entry:
115114
; CHECKASM32-NEXT: # %bb.0: # %entry
116115
; CHECKASM32-NEXT: mflr 0
117116
; CHECKASM32-NEXT: stwu 1, -64(1)
117+
; CHECKASM32-NEXT: li 3, 0
118118
; CHECKASM32-NEXT: li 4, 255
119119
; CHECKASM32-NEXT: stw 0, 72(1)
120120
; CHECKASM32-NEXT: bl .bar8
@@ -128,6 +128,7 @@ entry:
128128
; CHECKASM64-NEXT: # %bb.0: # %entry
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; CHECKASM64-NEXT: mflr 0
130130
; CHECKASM64-NEXT: stdu 1, -112(1)
131+
; CHECKASM64-NEXT: li 3, 0
131132
; CHECKASM64-NEXT: li 4, 255
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; CHECKASM64-NEXT: std 0, 128(1)
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; CHECKASM64-NEXT: bl .bar8
@@ -142,12 +143,12 @@ entry:
142143
; CHECKISEL64-NEXT: t1: i64 = GlobalAddress<ptr @bar8> 0
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; CHECKISEL64-NEXT: t2: i8 = poison
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; CHECKISEL64-NEXT: t3: i8 = Constant<-1>
145-
; CHECKISEL64-NEXT: t4: i32 = poison
146+
; CHECKISEL64-NEXT: t4: i32 = Constant<0>
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; CHECKISEL64-NEXT: t5: i32 = Constant<255>
147148
; CHECKISEL64-NEXT: t9: i64 = Register $x1
148149
; CHECKISEL64-NEXT: t0: ch,glue = EntryToken
149150
; CHECKISEL64-NEXT: t8: ch,glue = callseq_start t0, TargetConstant:i64<112>, TargetConstant:i64<0>
150-
; CHECKISEL64-NEXT: t13: ch,glue = CopyToReg t8, Register:i64 $x3, poison:i64
151+
; CHECKISEL64-NEXT: t13: ch,glue = CopyToReg t8, Register:i64 $x3, Constant:i64<0>
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; CHECKISEL64-NEXT: t15: ch,glue = CopyToReg t13, Register:i64 $x4, Constant:i64<255>, t13:1
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; CHECKISEL64-NEXT: t19: ch,glue = PPCISD::CALL_NOP t15, MCSymbol:i64, Register:i64 $x3, Register:i64 $x4, Register:i64 $x2, RegisterMask:Untyped, t15:1
153154
; CHECKISEL64-NEXT: t20: ch,glue = callseq_end t19, TargetConstant:i64<112>, TargetConstant:i64<0>, t19:1

‎llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,14 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 {
2727
; CHECK-NEXT: .cfi_remember_state
2828
; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: addi sp, sp, -32
30+
; CHECK-NEXT: li a0, 0
31+
; CHECK-NEXT: li a1, 0
32+
; CHECK-NEXT: li a2, 0
33+
; CHECK-NEXT: li a3, 0
34+
; CHECK-NEXT: li a4, 0
35+
; CHECK-NEXT: li a5, 0
36+
; CHECK-NEXT: li a6, 0
37+
; CHECK-NEXT: li a7, 0
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; CHECK-NEXT: call _Z3fooiiiiiiiiiiPi
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; CHECK-NEXT: addi sp, sp, 32
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; CHECK-NEXT: .Ltmp1:

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