Automerge: Revert bbc5221 "[DAGCombiner] Fold pattern for srl-shl-zext" (#139876)

Reverts llvm/llvm-project#138290 due to buildbot failures in shift-opt.ll

Author: RKSimon

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -10972,22 +10972,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
       return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
   }
 
-  // fold (srl (logic_op x, (shl (zext y), c1)), c1)
-  //   -> (logic_op (srl x, c1), (zext y))
-  // c1 <= leadingzeros(zext(y))
-  SDValue X, ZExtY;
-  if (N1C && sd_match(N0, m_OneUse(m_BitwiseLogic(
-                              m_Value(X),
-                              m_OneUse(m_Shl(m_AllOf(m_Value(ZExtY),
-                                                     m_Opc(ISD::ZERO_EXTEND)),
-                                             m_Specific(N1))))))) {
-    unsigned NumLeadingZeros = ZExtY.getScalarValueSizeInBits() -
-                               ZExtY.getOperand(0).getScalarValueSizeInBits();
-    if (N1C->getZExtValue() <= NumLeadingZeros)
-      return DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
-                         DAG.getNode(ISD::SRL, SDLoc(N0), VT, X, N1), ZExtY);
-  }
-
   // fold operands of srl based on knowledge that the low bits are not
   // demanded.
   if (SimplifyDemandedBits(SDValue(N, 0)))