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apply automated cargo clippy --fix
1 parent cb6f0de commit 82e2f0e

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+4
-4
lines changed

2 files changed

+4
-4
lines changed

src/native/delay.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ impl Future for Delay {
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return Poll::Ready(());
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}
118118

119-
state.waker.register(&cx.waker());
119+
state.waker.register(cx.waker());
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121121
// Now that we've registered, do the full check of our own internal
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// state. If we've fired the first bit is set, and if we've been

src/native/heap.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ impl<T: Ord> Heap<T> {
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6767
pub fn peek(&self) -> Option<&T> {
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self.assert_consistent();
69-
self.items.get(0).map(|i| &i.0)
69+
self.items.first().map(|i| &i.0)
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}
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7272
pub fn pop(&mut self) -> Option<T> {
@@ -191,7 +191,7 @@ impl<T: Ord> Heap<T> {
191191
}
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}
193193

194-
for (i, &(ref item, _)) in self.items.iter().enumerate() {
194+
for (i, (item, _)) in self.items.iter().enumerate() {
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if i > 0 {
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assert!(*item >= self.items[(i - 1) / 2].0, "bad at index: {}", i);
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}
@@ -272,7 +272,7 @@ mod tests {
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for t in v {
273273
h.push(t);
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}
275-
return h;
275+
h
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}
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#[test]

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