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ctopper
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[X86] Remove is the isVINSERT*Index/isVEXTRACT*Index predicates from isel.
The only insert_subvector/extract_subvector nodes that make it to isel are guaranteed to match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314058 91177308-0d34-0410-b5e6-96231b3b80d8
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3 files changed

+8
-78
lines changed

3 files changed

+8
-78
lines changed

lib/Target/X86/X86ISelLowering.cpp

Lines changed: 0 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -4809,51 +4809,6 @@ static bool canWidenShuffleElements(ArrayRef<int> Mask,
48094809
return true;
48104810
}
48114811

4812-
/// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4813-
/// extract that is suitable for instruction that extract 128 or 256 bit vectors
4814-
static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4815-
assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4816-
if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4817-
return false;
4818-
4819-
// The index should be aligned on a vecWidth-bit boundary.
4820-
uint64_t Index = N->getConstantOperandVal(1);
4821-
MVT VT = N->getSimpleValueType(0);
4822-
unsigned ElSize = VT.getScalarSizeInBits();
4823-
return (Index * ElSize) % vecWidth == 0;
4824-
}
4825-
4826-
/// Return true if the specified INSERT_SUBVECTOR
4827-
/// operand specifies a subvector insert that is suitable for input to
4828-
/// insertion of 128 or 256-bit subvectors
4829-
static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4830-
assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4831-
if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4832-
return false;
4833-
4834-
// The index should be aligned on a vecWidth-bit boundary.
4835-
uint64_t Index = N->getConstantOperandVal(2);
4836-
MVT VT = N->getSimpleValueType(0);
4837-
unsigned ElSize = VT.getScalarSizeInBits();
4838-
return (Index * ElSize) % vecWidth == 0;
4839-
}
4840-
4841-
bool X86::isVINSERT128Index(SDNode *N) {
4842-
return isVINSERTIndex(N, 128);
4843-
}
4844-
4845-
bool X86::isVINSERT256Index(SDNode *N) {
4846-
return isVINSERTIndex(N, 256);
4847-
}
4848-
4849-
bool X86::isVEXTRACT128Index(SDNode *N) {
4850-
return isVEXTRACTIndex(N, 128);
4851-
}
4852-
4853-
bool X86::isVEXTRACT256Index(SDNode *N) {
4854-
return isVEXTRACTIndex(N, 256);
4855-
}
4856-
48574812
static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
48584813
assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
48594814
assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&

lib/Target/X86/X86ISelLowering.h

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -624,26 +624,6 @@ namespace llvm {
624624

625625
/// Define some predicates that are used for node matching.
626626
namespace X86 {
627-
/// Return true if the specified
628-
/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
629-
/// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
630-
bool isVEXTRACT128Index(SDNode *N);
631-
632-
/// Return true if the specified
633-
/// INSERT_SUBVECTOR operand specifies a subvector insert that is
634-
/// suitable for input to VINSERTF128, VINSERTI128 instructions.
635-
bool isVINSERT128Index(SDNode *N);
636-
637-
/// Return true if the specified
638-
/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
639-
/// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
640-
bool isVEXTRACT256Index(SDNode *N);
641-
642-
/// Return true if the specified
643-
/// INSERT_SUBVECTOR operand specifies a subvector insert that is
644-
/// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
645-
bool isVINSERT256Index(SDNode *N);
646-
647627
/// Return the appropriate
648628
/// immediate to extract the specified EXTRACT_SUBVECTOR index
649629
/// with VEXTRACTF128, VEXTRACTI128 instructions.

lib/Target/X86/X86InstrFragmentsSIMD.td

Lines changed: 8 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -907,30 +907,25 @@ def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
907907

908908
def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
909909
(extract_subvector node:$bigvec,
910-
node:$index), [{
911-
return X86::isVEXTRACT128Index(N);
912-
}], EXTRACT_get_vextract128_imm>;
910+
node:$index), [{}],
911+
EXTRACT_get_vextract128_imm>;
913912

914913
def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
915914
node:$index),
916915
(insert_subvector node:$bigvec, node:$smallvec,
917-
node:$index), [{
918-
return X86::isVINSERT128Index(N);
919-
}], INSERT_get_vinsert128_imm>;
920-
916+
node:$index), [{}],
917+
INSERT_get_vinsert128_imm>;
921918

922919
def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
923920
(extract_subvector node:$bigvec,
924-
node:$index), [{
925-
return X86::isVEXTRACT256Index(N);
926-
}], EXTRACT_get_vextract256_imm>;
921+
node:$index), [{}],
922+
EXTRACT_get_vextract256_imm>;
927923

928924
def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
929925
node:$index),
930926
(insert_subvector node:$bigvec, node:$smallvec,
931-
node:$index), [{
932-
return X86::isVINSERT256Index(N);
933-
}], INSERT_get_vinsert256_imm>;
927+
node:$index), [{}],
928+
INSERT_get_vinsert256_imm>;
934929

935930
def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3),
936931
(masked_load node:$src1, node:$src2, node:$src3), [{

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