Skip to content

Commit 9c11776

Browse files
author
ctopper
committed
[InstCombine] Add test cases for known bits simplifications for comparisons that don't depend on constant RHS. NFC
This shows some missing simplifications for sge/sle/uge/ule relative to their non-equality counterparts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314031 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent d1642fb commit 9c11776

File tree

1 file changed

+143
-0
lines changed

1 file changed

+143
-0
lines changed

test/Transforms/InstCombine/icmp.ll

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3068,3 +3068,146 @@ define <8 x i1> @bitreverse_vec_ne(<8 x i16> %x, <8 x i16> %y) {
30683068
ret <8 x i1> %cmp
30693069
}
30703070

3071+
; These perform a comparison of a value known to be between 4 and 5 with a value between 5 and 7.
3072+
; They should all simplify to equality compares.
3073+
; FIXME this should simplify to an equality comparison
3074+
define i1 @knownbits1(i8 %a, i8 %b) {
3075+
; CHECK-LABEL: @knownbits1(
3076+
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3077+
; CHECK-NEXT: [[A2:%.*]] = or i8 [[A1]], 4
3078+
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3079+
; CHECK-NEXT: [[B2:%.*]] = or i8 [[B1]], 5
3080+
; CHECK-NEXT: [[C:%.*]] = icmp uge i8 [[A2]], [[B2]]
3081+
; CHECK-NEXT: ret i1 [[C]]
3082+
;
3083+
%a1 = and i8 %a, 5
3084+
%a2 = or i8 %a1, 4
3085+
%b1 = and i8 %b, 7
3086+
%b2 = or i8 %b1, 5
3087+
%c = icmp uge i8 %a2, %b2
3088+
ret i1 %c
3089+
}
3090+
3091+
define i1 @knownbits2(i8 %a, i8 %b) {
3092+
; CHECK-LABEL: @knownbits2(
3093+
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3094+
; CHECK-NEXT: [[A2:%.*]] = or i8 [[A1]], 4
3095+
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3096+
; CHECK-NEXT: [[B2:%.*]] = or i8 [[B1]], 5
3097+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A2]], [[B2]]
3098+
; CHECK-NEXT: ret i1 [[C]]
3099+
;
3100+
%a1 = and i8 %a, 5
3101+
%a2 = or i8 %a1, 4
3102+
%b1 = and i8 %b, 7
3103+
%b2 = or i8 %b1, 5
3104+
%c = icmp ult i8 %a2, %b2
3105+
ret i1 %c
3106+
}
3107+
3108+
; FIXME this should simplify to an equality comparison
3109+
define i1 @knownbits3(i8 %a, i8 %b) {
3110+
; CHECK-LABEL: @knownbits3(
3111+
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3112+
; CHECK-NEXT: [[A2:%.*]] = or i8 [[A1]], 4
3113+
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3114+
; CHECK-NEXT: [[B2:%.*]] = or i8 [[B1]], 5
3115+
; CHECK-NEXT: [[C:%.*]] = icmp ule i8 [[B2]], [[A2]]
3116+
; CHECK-NEXT: ret i1 [[C]]
3117+
;
3118+
%a1 = and i8 %a, 5
3119+
%a2 = or i8 %a1, 4
3120+
%b1 = and i8 %b, 7
3121+
%b2 = or i8 %b1, 5
3122+
%c = icmp ule i8 %b2, %a2
3123+
ret i1 %c
3124+
}
3125+
3126+
define <2 x i1> @knownbits4(<2 x i8> %a, <2 x i8> %b) {
3127+
; CHECK-LABEL: @knownbits4(
3128+
; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], <i8 1, i8 1>
3129+
; CHECK-NEXT: [[A2:%.*]] = or <2 x i8> [[A1]], <i8 4, i8 4>
3130+
; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], <i8 2, i8 2>
3131+
; CHECK-NEXT: [[B2:%.*]] = or <2 x i8> [[B1]], <i8 5, i8 5>
3132+
; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[B2]], [[A2]]
3133+
; CHECK-NEXT: ret <2 x i1> [[C]]
3134+
;
3135+
%a1 = and <2 x i8> %a, <i8 5, i8 5>
3136+
%a2 = or <2 x i8> %a1, <i8 4, i8 4>
3137+
%b1 = and <2 x i8> %b, <i8 7, i8 7>
3138+
%b2 = or <2 x i8> %b1, <i8 5, i8 5>
3139+
%c = icmp ugt <2 x i8> %b2, %a2
3140+
ret <2 x i1> %c
3141+
}
3142+
3143+
; These are the signed versions of the above. One value is less than or equal to 5, but maybe negative.
3144+
; The other is known to be a value 5-7. These should simplify to equality comparisons.
3145+
; FIXME this should simplify to an equality comparison
3146+
define i1 @knownbits5(i8 %a, i8 %b) {
3147+
; CHECK-LABEL: @knownbits5(
3148+
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
3149+
; CHECK-NEXT: [[A2:%.*]] = or i8 [[A1]], 4
3150+
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3151+
; CHECK-NEXT: [[B2:%.*]] = or i8 [[B1]], 5
3152+
; CHECK-NEXT: [[C:%.*]] = icmp sge i8 [[A2]], [[B2]]
3153+
; CHECK-NEXT: ret i1 [[C]]
3154+
;
3155+
%a1 = and i8 %a, 133
3156+
%a2 = or i8 %a1, 4
3157+
%b1 = and i8 %b, 7
3158+
%b2 = or i8 %b1, 5
3159+
%c = icmp sge i8 %a2, %b2
3160+
ret i1 %c
3161+
}
3162+
3163+
define i1 @knownbits6(i8 %a, i8 %b) {
3164+
; CHECK-LABEL: @knownbits6(
3165+
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
3166+
; CHECK-NEXT: [[A2:%.*]] = or i8 [[A1]], 4
3167+
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3168+
; CHECK-NEXT: [[B2:%.*]] = or i8 [[B1]], 5
3169+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A2]], [[B2]]
3170+
; CHECK-NEXT: ret i1 [[C]]
3171+
;
3172+
%a1 = and i8 %a, 133
3173+
%a2 = or i8 %a1, 4
3174+
%b1 = and i8 %b, 7
3175+
%b2 = or i8 %b1, 5
3176+
%c = icmp slt i8 %a2, %b2
3177+
ret i1 %c
3178+
}
3179+
3180+
; FIXME this should simplify to an equality comparison
3181+
define <2 x i1> @knownbits7(<2 x i8> %a, <2 x i8> %b) {
3182+
; CHECK-LABEL: @knownbits7(
3183+
; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], <i8 -127, i8 -127>
3184+
; CHECK-NEXT: [[A2:%.*]] = or <2 x i8> [[A1]], <i8 4, i8 4>
3185+
; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], <i8 2, i8 2>
3186+
; CHECK-NEXT: [[B2:%.*]] = or <2 x i8> [[B1]], <i8 5, i8 5>
3187+
; CHECK-NEXT: [[C:%.*]] = icmp sle <2 x i8> [[B2]], [[A2]]
3188+
; CHECK-NEXT: ret <2 x i1> [[C]]
3189+
;
3190+
%a1 = and <2 x i8> %a, <i8 133, i8 133>
3191+
%a2 = or <2 x i8> %a1, <i8 4, i8 4>
3192+
%b1 = and <2 x i8> %b, <i8 7, i8 7>
3193+
%b2 = or <2 x i8> %b1, <i8 5, i8 5>
3194+
%c = icmp sle <2 x i8> %b2, %a2
3195+
ret <2 x i1> %c
3196+
}
3197+
3198+
define i1 @knownbits8(i8 %a, i8 %b) {
3199+
; CHECK-LABEL: @knownbits8(
3200+
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
3201+
; CHECK-NEXT: [[A2:%.*]] = or i8 [[A1]], 4
3202+
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3203+
; CHECK-NEXT: [[B2:%.*]] = or i8 [[B1]], 5
3204+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[B2]], [[A2]]
3205+
; CHECK-NEXT: ret i1 [[C]]
3206+
;
3207+
%a1 = and i8 %a, 133
3208+
%a2 = or i8 %a1, 4
3209+
%b1 = and i8 %b, 7
3210+
%b2 = or i8 %b1, 5
3211+
%c = icmp sgt i8 %b2, %a2
3212+
ret i1 %c
3213+
}

0 commit comments

Comments
 (0)