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nickdesaulniersnickdesaulniers
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[RegAllocFast] NFC cleanups (llvm#74860)
- use more range for - avoid capturing lambda - prefer Register type to unsigned - remove braces around single statement if
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‎llvm/lib/CodeGen/RegAllocFast.cpp

Lines changed: 30 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -268,7 +268,7 @@ class RegAllocFast : public MachineFunctionPass {
268268
Register VirtReg);
269269
bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
270270
bool LookAtPhysRegUses = false);
271-
bool useVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg);
271+
bool useVirtReg(MachineInstr &MI, MachineOperand &MO, Register VirtReg);
272272

273273
MachineBasicBlock::iterator
274274
getMBBBeginInsertionPoint(MachineBasicBlock &MBB,
@@ -984,17 +984,15 @@ bool RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum,
984984

985985
/// Allocates a register for a VirtReg use.
986986
/// \return true if MI's MachineOperands were re-arranged/invalidated.
987-
bool RegAllocFast::useVirtReg(MachineInstr &MI, unsigned OpNum,
987+
bool RegAllocFast::useVirtReg(MachineInstr &MI, MachineOperand &MO,
988988
Register VirtReg) {
989989
assert(VirtReg.isVirtual() && "Not a virtual register");
990990
if (!shouldAllocateRegister(VirtReg))
991991
return false;
992-
MachineOperand &MO = MI.getOperand(OpNum);
993992
LiveRegMap::iterator LRI;
994993
bool New;
995994
std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
996995
if (New) {
997-
MachineOperand &MO = MI.getOperand(OpNum);
998996
if (!MO.isKill()) {
999997
if (mayLiveOut(VirtReg)) {
1000998
LRI->LiveOut = true;
@@ -1224,6 +1222,17 @@ void RegAllocFast::findAndSortDefOperandIndexes(const MachineInstr &MI) {
12241222
});
12251223
}
12261224

1225+
// Returns true if MO is tied and the operand it's tied to is not Undef (not
1226+
// Undef is not the same thing as Def).
1227+
static bool isTiedToNotUndef(const MachineOperand &MO) {
1228+
if (!MO.isTied())
1229+
return false;
1230+
const MachineInstr &MI = *MO.getParent();
1231+
unsigned TiedIdx = MI.findTiedOperandIdx(MI.getOperandNo(&MO));
1232+
const MachineOperand &TiedMO = MI.getOperand(TiedIdx);
1233+
return !TiedMO.isUndef();
1234+
}
1235+
12271236
void RegAllocFast::allocateInstruction(MachineInstr &MI) {
12281237
// The basic algorithm here is:
12291238
// 1. Mark registers of def operands as free
@@ -1241,21 +1250,14 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
12411250
RegMasks.clear();
12421251
BundleVirtRegsMap.clear();
12431252

1244-
auto TiedOpIsUndef = [&](const MachineOperand &MO, unsigned Idx) {
1245-
assert(MO.isTied());
1246-
unsigned TiedIdx = MI.findTiedOperandIdx(Idx);
1247-
const MachineOperand &TiedMO = MI.getOperand(TiedIdx);
1248-
return TiedMO.isUndef();
1249-
};
12501253
// Scan for special cases; Apply pre-assigned register defs to state.
12511254
bool HasPhysRegUse = false;
12521255
bool HasRegMask = false;
12531256
bool HasVRegDef = false;
12541257
bool HasDef = false;
12551258
bool HasEarlyClobber = false;
12561259
bool NeedToAssignLiveThroughs = false;
1257-
for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
1258-
MachineOperand &MO = MI.getOperand(I);
1260+
for (MachineOperand &MO : MI.operands()) {
12591261
if (MO.isReg()) {
12601262
Register Reg = MO.getReg();
12611263
if (Reg.isVirtual()) {
@@ -1268,8 +1270,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
12681270
HasEarlyClobber = true;
12691271
NeedToAssignLiveThroughs = true;
12701272
}
1271-
if ((MO.isTied() && !TiedOpIsUndef(MO, I)) ||
1272-
(MO.getSubReg() != 0 && !MO.isUndef()))
1273+
if (isTiedToNotUndef(MO) || (MO.getSubReg() != 0 && !MO.isUndef()))
12731274
NeedToAssignLiveThroughs = true;
12741275
}
12751276
} else if (Reg.isPhysical()) {
@@ -1314,35 +1315,32 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
13141315
for (uint16_t OpIdx : DefOperandIndexes) {
13151316
MachineOperand &MO = MI.getOperand(OpIdx);
13161317
LLVM_DEBUG(dbgs() << "Allocating " << MO << '\n');
1317-
unsigned Reg = MO.getReg();
1318-
if (MO.isEarlyClobber() ||
1319-
(MO.isTied() && !TiedOpIsUndef(MO, OpIdx)) ||
1318+
Register Reg = MO.getReg();
1319+
if (MO.isEarlyClobber() || isTiedToNotUndef(MO) ||
13201320
(MO.getSubReg() && !MO.isUndef())) {
13211321
ReArrangedImplicitOps = defineLiveThroughVirtReg(MI, OpIdx, Reg);
13221322
} else {
13231323
ReArrangedImplicitOps = defineVirtReg(MI, OpIdx, Reg);
13241324
}
1325-
if (ReArrangedImplicitOps) {
1326-
// Implicit operands of MI were re-arranged,
1327-
// re-compute DefOperandIndexes.
1325+
// Implicit operands of MI were re-arranged,
1326+
// re-compute DefOperandIndexes.
1327+
if (ReArrangedImplicitOps)
13281328
break;
1329-
}
13301329
}
13311330
}
13321331
} else {
13331332
// Assign virtual register defs.
13341333
while (ReArrangedImplicitOps) {
13351334
ReArrangedImplicitOps = false;
1336-
for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
1337-
MachineOperand &MO = MI.getOperand(I);
1335+
for (MachineOperand &MO : MI.operands()) {
13381336
if (!MO.isReg() || !MO.isDef())
13391337
continue;
13401338
Register Reg = MO.getReg();
13411339
if (Reg.isVirtual()) {
1342-
ReArrangedImplicitOps = defineVirtReg(MI, I, Reg);
1343-
if (ReArrangedImplicitOps) {
1340+
ReArrangedImplicitOps =
1341+
defineVirtReg(MI, MI.getOperandNo(&MO), Reg);
1342+
if (ReArrangedImplicitOps)
13441343
break;
1345-
}
13461344
}
13471345
}
13481346
}
@@ -1352,8 +1350,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
13521350
// Free registers occupied by defs.
13531351
// Iterate operands in reverse order, so we see the implicit super register
13541352
// defs first (we added them earlier in case of <def,read-undef>).
1355-
for (signed I = MI.getNumOperands() - 1; I >= 0; --I) {
1356-
MachineOperand &MO = MI.getOperand(I);
1353+
for (MachineOperand &MO : reverse(MI.operands())) {
13571354
if (!MO.isReg() || !MO.isDef())
13581355
continue;
13591356

@@ -1370,7 +1367,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
13701367
"tied def assigned to clobbered register");
13711368

13721369
// Do not free tied operands and early clobbers.
1373-
if ((MO.isTied() && !TiedOpIsUndef(MO, I)) || MO.isEarlyClobber())
1370+
if (isTiedToNotUndef(MO) || MO.isEarlyClobber())
13741371
continue;
13751372
if (!Reg)
13761373
continue;
@@ -1411,8 +1408,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
14111408
continue;
14121409
if (MRI->isReserved(Reg))
14131410
continue;
1414-
bool displacedAny = usePhysReg(MI, Reg);
1415-
if (!displacedAny)
1411+
if (!usePhysReg(MI, Reg))
14161412
MO.setIsKill(true);
14171413
}
14181414
}
@@ -1424,8 +1420,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
14241420
bool ReArrangedImplicitMOs = true;
14251421
while (ReArrangedImplicitMOs) {
14261422
ReArrangedImplicitMOs = false;
1427-
for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
1428-
MachineOperand &MO = MI.getOperand(I);
1423+
for (MachineOperand &MO : MI.operands()) {
14291424
if (!MO.isReg() || !MO.isUse())
14301425
continue;
14311426
Register Reg = MO.getReg();
@@ -1443,7 +1438,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
14431438

14441439
assert(!MO.isInternalRead() && "Bundles not supported");
14451440
assert(MO.readsReg() && "reading use");
1446-
ReArrangedImplicitMOs = useVirtReg(MI, I, Reg);
1441+
ReArrangedImplicitMOs = useVirtReg(MI, MO, Reg);
14471442
if (ReArrangedImplicitMOs)
14481443
break;
14491444
}
@@ -1465,7 +1460,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
14651460

14661461
// Free early clobbers.
14671462
if (HasEarlyClobber) {
1468-
for (MachineOperand &MO : llvm::reverse(MI.all_defs())) {
1463+
for (MachineOperand &MO : reverse(MI.all_defs())) {
14691464
if (!MO.isEarlyClobber())
14701465
continue;
14711466
assert(!MO.getSubReg() && "should be already handled in def processing");

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