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Merge pull request swiftlang#14651 from aschwaighofer/enable_thumbv7_again
Use clang's effective llvm triple for IR generation
2 parents 33996de + 2d58f08 commit d3ad4ed

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10 files changed

+103
-58
lines changed

10 files changed

+103
-58
lines changed

‎include/swift/Subsystems.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -248,8 +248,9 @@ namespace swift {
248248
void serialize(ModuleOrSourceFile DC, const SerializationOptions &options,
249249
const SILModule *M = nullptr);
250250

251-
/// Get the CPU and subtarget feature options to use when emitting code.
252-
std::tuple<llvm::TargetOptions, std::string, std::vector<std::string>>
251+
/// Get the CPU, subtarget feature options, and triple to use when emitting code.
252+
std::tuple<llvm::TargetOptions, std::string, std::vector<std::string>,
253+
std::string>
253254
getIRTargetOptions(IRGenOptions &Opts, ASTContext &Ctx);
254255

255256
/// Turn the given Swift module into either LLVM IR or native code

‎lib/IRGen/IRGen.cpp

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -127,7 +127,8 @@ static void addSanitizerCoveragePass(const PassManagerBuilder &Builder,
127127
BuilderWrapper.IRGOpts.SanitizeCoverage));
128128
}
129129

130-
std::tuple<llvm::TargetOptions, std::string, std::vector<std::string>>
130+
std::tuple<llvm::TargetOptions, std::string, std::vector<std::string>,
131+
std::string>
131132
swift::getIRTargetOptions(IRGenOptions &Opts, ASTContext &Ctx) {
132133
// Things that maybe we should collect from the command line:
133134
// - relocation model
@@ -141,7 +142,7 @@ swift::getIRTargetOptions(IRGenOptions &Opts, ASTContext &Ctx) {
141142

142143
auto *Clang = static_cast<ClangImporter *>(Ctx.getClangModuleLoader());
143144
clang::TargetOptions &ClangOpts = Clang->getTargetInfo().getTargetOpts();
144-
return std::make_tuple(TargetOpts, ClangOpts.CPU, ClangOpts.Features);
145+
return std::make_tuple(TargetOpts, ClangOpts.CPU, ClangOpts.Features, ClangOpts.Triple);
145146
}
146147

147148
void setModuleFlags(IRGenModule &IGM) {
@@ -520,24 +521,18 @@ bool swift::performLLVM(IRGenOptions &Opts, DiagnosticEngine *Diags,
520521

521522
std::unique_ptr<llvm::TargetMachine>
522523
swift::createTargetMachine(IRGenOptions &Opts, ASTContext &Ctx) {
523-
const llvm::Triple &Triple = Ctx.LangOpts.Target;
524-
std::string Error;
525-
const Target *Target = TargetRegistry::lookupTarget(Triple.str(), Error);
526-
if (!Target) {
527-
Ctx.Diags.diagnose(SourceLoc(), diag::no_llvm_target, Triple.str(), Error);
528-
return nullptr;
529-
}
530-
531-
CodeGenOpt::Level OptLevel = (Opts.shouldOptimize() ?
532-
CodeGenOpt::Default // -Os
533-
: CodeGenOpt::None);
524+
CodeGenOpt::Level OptLevel = Opts.shouldOptimize()
525+
? CodeGenOpt::Default // -Os
526+
: CodeGenOpt::None;
534527

535528
// Set up TargetOptions and create the target features string.
536529
TargetOptions TargetOpts;
537530
std::string CPU;
531+
std::string EffectiveClangTriple;
538532
std::vector<std::string> targetFeaturesArray;
539-
std::tie(TargetOpts, CPU, targetFeaturesArray)
533+
std::tie(TargetOpts, CPU, targetFeaturesArray, EffectiveClangTriple)
540534
= getIRTargetOptions(Opts, Ctx);
535+
const llvm::Triple &EffectiveTriple = llvm::Triple(EffectiveClangTriple);
541536
std::string targetFeatures;
542537
if (!targetFeaturesArray.empty()) {
543538
llvm::SubtargetFeatures features;
@@ -548,13 +543,23 @@ swift::createTargetMachine(IRGenOptions &Opts, ASTContext &Ctx) {
548543
targetFeatures = features.getString();
549544
}
550545

546+
std::string Error;
547+
const Target *Target =
548+
TargetRegistry::lookupTarget(EffectiveTriple.str(), Error);
549+
if (!Target) {
550+
Ctx.Diags.diagnose(SourceLoc(), diag::no_llvm_target, EffectiveTriple.str(),
551+
Error);
552+
return nullptr;
553+
}
554+
555+
551556
// Create a target machine.
552-
llvm::TargetMachine *TargetMachine =
553-
Target->createTargetMachine(Triple.str(), CPU, targetFeatures, TargetOpts,
554-
Reloc::PIC_, CodeModel::Default, OptLevel);
557+
llvm::TargetMachine *TargetMachine = Target->createTargetMachine(
558+
EffectiveTriple.str(), CPU, targetFeatures, TargetOpts, Reloc::PIC_,
559+
CodeModel::Default, OptLevel);
555560
if (!TargetMachine) {
556561
Ctx.Diags.diagnose(SourceLoc(), diag::no_llvm_target,
557-
Triple.str(), "no LLVM target machine");
562+
EffectiveTriple.str(), "no LLVM target machine");
558563
return nullptr;
559564
}
560565
return std::unique_ptr<llvm::TargetMachine>(TargetMachine);

‎lib/IRGen/IRGenModule.cpp

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -130,9 +130,9 @@ IRGenModule::IRGenModule(IRGenerator &irgen,
130130
ClangCodeGen(createClangCodeGenerator(Context, LLVMContext, irgen.Opts,
131131
ModuleName)),
132132
Module(*ClangCodeGen->GetModule()), LLVMContext(Module.getContext()),
133-
DataLayout(target->createDataLayout()), Triple(Context.LangOpts.Target),
134-
TargetMachine(std::move(target)), silConv(irgen.SIL),
135-
OutputFilename(OutputFilename),
133+
DataLayout(target->createDataLayout()),
134+
Triple(irgen.getEffectiveClangTriple()), TargetMachine(std::move(target)),
135+
silConv(irgen.SIL), OutputFilename(OutputFilename),
136136
TargetInfo(SwiftTargetInfo::get(*this)), DebugInfo(nullptr),
137137
ModuleHash(nullptr), ObjCInterop(Context.LangOpts.EnableObjCInterop),
138138
UseDarwinPreStableABIBit(Context.LangOpts.UseDarwinPreStableABIBit),
@@ -1120,3 +1120,10 @@ IRGenModule *IRGenerator::getGenModule(SILFunction *f) {
11201120

11211121
return getPrimaryIGM();
11221122
}
1123+
1124+
llvm::Triple IRGenerator::getEffectiveClangTriple() {
1125+
auto CI = static_cast<ClangImporter *>(
1126+
&*SIL.getASTContext().getClangModuleLoader());
1127+
assert(CI && "no clang module loader");
1128+
return llvm::Triple(CI->getTargetInfo().getTargetOpts().Triple);
1129+
}

‎lib/IRGen/IRGenModule.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -389,6 +389,9 @@ class IRGenerator {
389389
}
390390
return nullptr;
391391
}
392+
393+
/// Return the effective triple used by clang.
394+
llvm::Triple getEffectiveClangTriple();
392395
};
393396

394397
class ConstantReference {
@@ -427,7 +430,7 @@ class IRGenModule {
427430
llvm::Module &Module;
428431
llvm::LLVMContext &LLVMContext;
429432
const llvm::DataLayout DataLayout;
430-
const llvm::Triple &Triple;
433+
const llvm::Triple Triple;
431434
std::unique_ptr<llvm::TargetMachine> TargetMachine;
432435
ModuleDecl *getSwiftModule() const;
433436
Lowering::TypeConverter &getSILTypes() const;

‎lib/Immediate/Immediate.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -359,8 +359,9 @@ int swift::RunImmediately(CompilerInstance &CI, const ProcessCmdLine &CmdLine,
359359
std::string ErrorMsg;
360360
llvm::TargetOptions TargetOpt;
361361
std::string CPU;
362+
std::string Triple;
362363
std::vector<std::string> Features;
363-
std::tie(TargetOpt, CPU, Features)
364+
std::tie(TargetOpt, CPU, Features, Triple)
364365
= getIRTargetOptions(IRGenOpts, swiftModule->getASTContext());
365366
builder.setRelocationModel(llvm::Reloc::PIC_);
366367
builder.setTargetOptions(TargetOpt);

‎lib/Immediate/REPL.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -989,8 +989,9 @@ class REPLEnvironment {
989989
std::string ErrorMsg;
990990
llvm::TargetOptions TargetOpt;
991991
std::string CPU;
992+
std::string Triple;
992993
std::vector<std::string> Features;
993-
std::tie(TargetOpt, CPU, Features)
994+
std::tie(TargetOpt, CPU, Features, Triple)
994995
= getIRTargetOptions(IRGenOpts, CI.getASTContext());
995996

996997
builder.setRelocationModel(llvm::Reloc::PIC_);

‎test/IRGen/abi_v7k.swift

Lines changed: 24 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ func testEmpty(x: Empty) -> Empty {
6868
// CHECK-LABEL: define hidden swiftcc i32 @"$S8test_v7k0A6Single{{.*}}"()
6969
// CHECK: ret i32 1
7070
// V7K-LABEL: _$S8test_v7k0A6Single
71-
// V7K: movw r0, #1
71+
// V7K: movs r0, #1
7272
enum SingleCase { case X }
7373
func testSingle(x: SingleCase) -> Int32{
7474
switch x {
@@ -94,9 +94,9 @@ func testData(x: DataCase) -> Double {
9494
// CHECK: [[ID:%[0-9]+]] = phi i32 [ 2, {{.*}} ], [ 1, {{.*}} ]
9595
// CHECK: ret i32 [[ID]]
9696
// V7K-LABEL: _$S8test_v7k0A6Clike2
97-
// V7K: tst r0, #1
98-
// V7K: movw r0, #1
99-
// V7K: movw r0, #2
97+
// V7K: tst.w r0, #1
98+
// V7K: movs r0, #1
99+
// V7K: movs r0, #2
100100
enum CLike2 {
101101
case A
102102
case B
@@ -116,7 +116,7 @@ func testClike2(x: CLike2) -> Int {
116116
// V7K-LABEL: _$S8test_v7k0A6Clike8
117117
// V7K: sxtb r1, r1
118118
// V7K: cmp r1, #0
119-
// V7K: movw r0, #1
119+
// V7K: movs r0, #1
120120
// V7K: mvn r0, #0
121121
enum CLike8 {
122122
case A
@@ -149,7 +149,7 @@ func testClike8(t: Int, x: CLike8) -> Int {
149149
// CHECK: bitcast i64 [[RESULT]] to double
150150
// CHECK: phi double [ 0.000000e+00, {{.*}} ]
151151
// V7K-LABEL: _$S8test_v7k0A7SingleP
152-
// V7K: tst r2, #1
152+
// V7K: tst.w r2, #1
153153
// V7K: vmov.f64 d0
154154
enum SinglePayload {
155155
case Paragraph
@@ -202,12 +202,12 @@ func testMultiP(x: MultiPayload) -> Double {
202202
// CHECK: [[ID:%[0-9]+]] = bitcast i32 %0 to float
203203
// CHECK: ret float
204204
// V7K-LABEL: _$S8test_v7k0A3Opt
205-
// V7K: tst r1, #1
206-
// V7K: str r0, [r7, [[SLOT:#-[0-9]+]]
207-
// V7K: ldr r0, [r7, [[SLOT]]
205+
// V7K: tst.w r1, #1
206+
// V7K: str r0, [sp, [[SLOT:#[0-9]+]]
207+
// V7K: ldr r0, [sp, [[SLOT]]
208208
// V7K: vmov s0, r0
209-
// V7K: vstr s0, [r7, [[SLOT2:#-[0-9]+]]
210-
// V7K: vldr s0, [r7, [[SLOT2]]
209+
// V7K: vstr s0, [sp, [[SLOT2:#[0-9]+]]
210+
// V7K: vldr s0, [sp, [[SLOT2]]
211211
// V7K: pop {{{.*}}, pc}
212212
func testOpt(x: Float?) -> Float {
213213
return x!
@@ -291,9 +291,9 @@ func testRet3() -> MyRect2 {
291291
// V7K: cmp r1, r2
292292
// V7K: str r0, [sp, [[IDX:#[0-9]+]]]
293293
// V7K: ldr [[R0_RELOAD:r[0-9]+]], [sp, [[IDX]]]
294-
// V7K: str {{.*}}, [{{.*}}[[R0_RELOAD]]]
295-
// V7K: str {{.*}}, [{{.*}}[[R0_RELOAD]], #4]
296-
// V7K: str {{.*}}, [{{.*}}[[R0_RELOAD]], #8]
294+
// V7K: str.w {{.*}}, [{{.*}}[[R0_RELOAD]]]
295+
// V7K: str.w {{.*}}, [{{.*}}[[R0_RELOAD]], #4]
296+
// V7K: str.w {{.*}}, [{{.*}}[[R0_RELOAD]], #8]
297297
// V7K: str {{.*}}, [{{.*}}[[R0_RELOAD]], #12]
298298
// V7K: str {{.*}}, [{{.*}}[[R0_RELOAD]], #16]
299299
// V7K: str {{.*}}, [{{.*}}[[R0_RELOAD]], #20]
@@ -338,12 +338,11 @@ func minMax3(x : Int, y : Int) -> Ret? {
338338
// Passing struct: Int8, MyPoint x 10, MySize * 10
339339
// CHECK-LABEL: define hidden swiftcc double @"$S8test_v7k0A4Ret5{{.*}}"(%T8test_v7k7MyRect3V* noalias nocapture dereferenceable(328))
340340
// V7K-LABEL: _$S8test_v7k0A4Ret5
341-
// V7K: sub sp, sp, #56
342-
// V7K: ldrb r1, [r0]
343-
// V7K: strb r1, [sp, #52]
344-
// V7K: ldrsb r1, [sp, #52]
345-
// V7K: vmov s0, r1
346-
// V7K: vcvt.f64.s32 d16, s0
341+
// V7K: ldrb r1, [r0]
342+
// V7K: strb.w r1, [sp, #52]
343+
// V7K: ldrsb.w r1, [sp, #52]
344+
// V7K: vmov s0, r1
345+
// V7K: vcvt.f64.s32 d16, s0
347346
// V7K: ldr r1, [r0, #8]
348347
// V7K: str r1, [sp, #24]
349348
// V7K: ldr r1, [r0, #12]
@@ -358,21 +357,21 @@ func minMax3(x : Int, y : Int) -> Ret? {
358357
// V7K: str r1, [sp, #44]
359358
// V7K: vldr d18, [sp, #40]
360359
// V7K: vadd.f64 d16, d16, d18
361-
// V7K: ldr r1, [r0, #296]
360+
// V7K: ldr.w r1, [r0, #296]
362361
// V7K: str r1, [sp]
363-
// V7K: ldr r1, [r0, #300]
362+
// V7K: ldr.w r1, [r0, #300]
364363
// V7K: str r1, [sp, #4]
365-
// V7K: ldr r1, [r0, #304]
364+
// V7K: ldr.w r1, [r0, #304]
366365
// V7K: str r1, [sp, #8]
367-
// V7K: ldr r0, [r0, #308]
366+
// V7K: ldr.w r0, [r0, #308]
368367
// V7K: str r0, [sp, #12]
369368
// V7K: ldr r0, [sp]
370369
// V7K: str r0, [sp, #16]
371370
// V7K: ldr r0, [sp, #4]
372371
// V7K: str r0, [sp, #20]
373372
// V7K: vldr d18, [sp, #16]
374373
// V7K: vadd.f64 d0, d16, d18
375-
// V7K: add sp, sp, #56
374+
// V7K: add sp, #56
376375
// V7K: bx lr
377376

378377
struct MyRect3 {

‎test/IRGen/arm_to_thumb_darwin.sil

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
// RUN: %swift -target armv7-apple-ios7 %s -gnone -emit-ir -o - | %FileCheck %s -check-prefix=IOS
2+
// RUN: %swift -target armv7k-apple-watchos2 %s -gnone -emit-ir -o - | %FileCheck %s -check-prefix=WATCHOS
3+
4+
// REQUIRES: CODEGENERATOR=ARM
5+
6+
sil_stage canonical
7+
import Builtin
8+
9+
// IOS: target triple = "thumbv7-apple-ios7
10+
11+
// IOS: define{{( protected)?}} swiftcc i32 @word_literal() {{.*}} {
12+
// IOS: entry:
13+
// IOS: ret i32 12345
14+
// IOS: }
15+
16+
17+
// WATCHOS: target triple = "thumbv7k-apple-watchos2
18+
19+
// WATCHOS: define{{( protected)?}} swiftcc i32 @word_literal() {{.*}} {
20+
// WATCHOS: entry:
21+
// WATCHOS: ret i32 12345
22+
// WATCHOS: }
23+
24+
sil @word_literal : $() -> Builtin.Word {
25+
entry:
26+
%w = integer_literal $Builtin.Word, 12345
27+
return %w : $Builtin.Word
28+
}

‎test/IRGen/osx-targets.swift

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
// REQUIRES: OS=macosx
66

77
// CHECK: target triple = "x86_64-apple-macosx10.
8-
// CHECK-SPECIFIC: target triple = "x86_64-apple-macosx10.12"
8+
// CHECK-SPECIFIC: target triple = "x86_64-apple-macosx10.12.0"
99

1010
public func anchor() {}
1111
anchor()

‎test/IRGen/pic.swift

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -23,24 +23,24 @@ public func use_global() -> Int {
2323
// Check for the runtime memory enforcement call. The global address may be
2424
// materialized in a different register prior to that call.
2525
// armv7: bl _swift_beginAccess
26-
// armv7: movw [[R_ADR:r.*]], :lower16:(_$S4main6globalSivp-([[PIC_0:L.*]]+8))
27-
// armv7: movt [[R_ADR]], :upper16:(_$S4main6globalSivp-([[PIC_0]]+8))
26+
// armv7: movw [[R_ADR:r.*]], :lower16:(_$S4main6globalSivp-([[PIC_0:L.*]]+4))
27+
// armv7: movt [[R_ADR]], :upper16:(_$S4main6globalSivp-([[PIC_0]]+4))
2828
// armv7: [[PIC_0]]:{{$}}
2929
// armv7: add [[R_ADR]], pc
3030
// armv7: ldr [[R_ADR]], {{\[}}[[R_ADR]]{{\]}}
3131

3232
// armv7s-LABEL: _$S4main10use_globalSiyF:
3333
// armv7s: bl _swift_beginAccess
34-
// armv7s: movw [[R_ADR:r.*]], :lower16:(_$S4main6globalSivp-([[PIC_0:L.*]]+8))
35-
// armv7s: movt [[R_ADR]], :upper16:(_$S4main6globalSivp-([[PIC_0]]+8))
34+
// armv7s: movw [[R_ADR:r.*]], :lower16:(_$S4main6globalSivp-([[PIC_0:L.*]]+4))
35+
// armv7s: movt [[R_ADR]], :upper16:(_$S4main6globalSivp-([[PIC_0]]+4))
3636
// armv7s: [[PIC_0]]:{{$}}
3737
// armv7s: add [[R_ADR]], pc
3838
// armv7s: ldr [[R_ADR]], {{\[}}[[R_ADR]]{{\]}}
3939

4040
// armv7k-LABEL: _$S4main10use_globalSiyF:
4141
// armv7k: bl _swift_beginAccess
42-
// armv7k: movw [[R_ADR:r.*]], :lower16:(_$S4main6globalSivp-([[PIC_0:L.*]]+8))
43-
// armv7k: movt [[R_ADR]], :upper16:(_$S4main6globalSivp-([[PIC_0]]+8))
42+
// armv7k: movw [[R_ADR:r.*]], :lower16:(_$S4main6globalSivp-([[PIC_0:L.*]]+4))
43+
// armv7k: movt [[R_ADR]], :upper16:(_$S4main6globalSivp-([[PIC_0]]+4))
4444
// armv7k: [[PIC_0]]:{{$}}
4545
// armv7k: add [[R_ADR]], pc
4646
// armv7k: ldr [[R_ADR]], {{\[}}[[R_ADR]]{{\]}}

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