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[NFC][LLVM][SVE][ISel] Remove redundant type information from Pat targets. (llvm#85409)
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 62 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -2042,9 +2042,8 @@ let Predicates = [HasSVEorSME] in {
20422042
defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp", int_aarch64_sve_cntp>;
20432043

20442044
def : Pat<(i64 (AArch64CttzElts nxv16i1:$Op1)),
2045-
(i64 (!cast<Instruction>(CNTP_XPP_B)
2046-
(nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op1)),
2047-
(nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op1))))>;
2045+
(CNTP_XPP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op1),
2046+
(BRKB_PPzP (PTRUE_B 31), PPR:$Op1))>;
20482047
}
20492048

20502049
defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb", add, int_aarch64_sve_cntb>;
@@ -2131,15 +2130,12 @@ let Predicates = [HasSVEorSME] in {
21312130
defm DECP_ZP : sve_int_count_v<0b10100, "decp">;
21322131

21332132
def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv16i1:$Op2)))),
2134-
(i64 (!cast<Instruction>(INCP_XP_B)
2135-
(nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op2)),
2136-
GPR64:$Op1))>;
2133+
(INCP_XP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op2), GPR64:$Op1)>;
21372134

21382135
def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv16i1:$Op2))))),
2139-
(i32 (EXTRACT_SUBREG (i64 (!cast<Instruction>(INCP_XP_B)
2140-
(nxv16i1 (!cast<Instruction>(BRKB_PPzP) (PTRUE_B 31), nxv16i1:$Op2)),
2141-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Op1, sub_32))),
2142-
sub_32))>;
2136+
(EXTRACT_SUBREG (INCP_XP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op2),
2137+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Op1, sub_32)),
2138+
sub_32)>;
21432139

21442140
defm INDEX_RR : sve_int_index_rr<"index", AArch64mul_p_oneuse>;
21452141
defm INDEX_IR : sve_int_index_ir<"index", AArch64mul_p, AArch64mul_p_oneuse>;
@@ -2521,9 +2517,9 @@ let Predicates = [HasSVEorSME] in {
25212517
(ADDVL_XXI GPR64:$op, $imm)>;
25222518

25232519
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_rdvl_imm i32:$imm))))),
2524-
(i32 (EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2525-
GPR32:$op, sub_32), $imm),
2526-
sub_32))>;
2520+
(EXTRACT_SUBREG (ADDVL_XXI (INSERT_SUBREG (IMPLICIT_DEF),
2521+
GPR32:$op, sub_32), $imm),
2522+
sub_32)>;
25272523

25282524
def : Pat<(add GPR64:$op, (vscale (sve_cnth_imm i32:$imm))),
25292525
(INCH_XPiI GPR64:$op, 31, $imm)>;
@@ -2540,30 +2536,30 @@ let Predicates = [HasSVEorSME] in {
25402536
(DECD_XPiI GPR64:$op, 31, $imm)>;
25412537

25422538
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cnth_imm i32:$imm))))),
2543-
(i32 (EXTRACT_SUBREG (INCH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2544-
GPR32:$op, sub_32), 31, $imm),
2545-
sub_32))>;
2539+
(EXTRACT_SUBREG (INCH_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
2540+
GPR32:$op, sub_32), 31, $imm),
2541+
sub_32)>;
25462542
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntw_imm i32:$imm))))),
2547-
(i32 (EXTRACT_SUBREG (INCW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2548-
GPR32:$op, sub_32), 31, $imm),
2549-
sub_32))>;
2543+
(EXTRACT_SUBREG (INCW_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
2544+
GPR32:$op, sub_32), 31, $imm),
2545+
sub_32)>;
25502546
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntd_imm i32:$imm))))),
2551-
(i32 (EXTRACT_SUBREG (INCD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2552-
GPR32:$op, sub_32), 31, $imm),
2553-
sub_32))>;
2547+
(EXTRACT_SUBREG (INCD_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
2548+
GPR32:$op, sub_32), 31, $imm),
2549+
sub_32)>;
25542550

25552551
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cnth_imm_neg i32:$imm))))),
2556-
(i32 (EXTRACT_SUBREG (DECH_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2557-
GPR32:$op, sub_32), 31, $imm),
2558-
sub_32))>;
2552+
(EXTRACT_SUBREG (DECH_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
2553+
GPR32:$op, sub_32), 31, $imm),
2554+
sub_32)>;
25592555
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntw_imm_neg i32:$imm))))),
2560-
(i32 (EXTRACT_SUBREG (DECW_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2561-
GPR32:$op, sub_32), 31, $imm),
2562-
sub_32))>;
2556+
(EXTRACT_SUBREG (DECW_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
2557+
GPR32:$op, sub_32), 31, $imm),
2558+
sub_32)>;
25632559
def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntd_imm_neg i32:$imm))))),
2564-
(i32 (EXTRACT_SUBREG (DECD_XPiI (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2565-
GPR32:$op, sub_32), 31, $imm),
2566-
sub_32))>;
2560+
(EXTRACT_SUBREG (DECD_XPiI (INSERT_SUBREG (IMPLICIT_DEF),
2561+
GPR32:$op, sub_32), 31, $imm),
2562+
sub_32)>;
25672563
}
25682564

25692565
// FIXME: BigEndian requires an additional REV instruction to satisfy the
@@ -3266,58 +3262,58 @@ let Predicates = [HasSVEorSME] in {
32663262
// Extract element from vector with immediate index that's within the bottom 128-bits.
32673263
let Predicates = [IsNeonAvailable], AddedComplexity = 1 in {
32683264
def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index)),
3269-
(i32 (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
3265+
(UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
32703266
def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index)),
3271-
(i32 (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index))>;
3267+
(UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
32723268
def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index)),
3273-
(i32 (UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index))>;
3269+
(UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
32743270
def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), VectorIndexD:$index)),
3275-
(i64 (UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index))>;
3271+
(UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>;
32763272
} // End IsNeonAvailable
32773273

32783274
let Predicates = [IsNeonAvailable] in {
32793275
def : Pat<(sext_inreg (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index), i8),
3280-
(i32 (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
3276+
(SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
32813277
def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index))), i8),
3282-
(i64 (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index))>;
3278+
(SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
32833279

32843280
def : Pat<(sext_inreg (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index), i16),
3285-
(i32 (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index))>;
3281+
(SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
32863282
def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index))), i16),
3287-
(i64 (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index))>;
3283+
(SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
32883284

32893285
def : Pat<(sext (i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index))),
3290-
(i64 (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index))>;
3286+
(SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
32913287
} // End IsNeonAvailable
32923288

32933289
// Extract first element from vector.
32943290
let AddedComplexity = 2 in {
3295-
def : Pat<(vector_extract (nxv16i8 ZPR:$Zs), (i64 0)),
3296-
(i32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
3297-
def : Pat<(vector_extract (nxv8i16 ZPR:$Zs), (i64 0)),
3298-
(i32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
3299-
def : Pat<(vector_extract (nxv4i32 ZPR:$Zs), (i64 0)),
3300-
(i32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
3301-
def : Pat<(vector_extract (nxv2i64 ZPR:$Zs), (i64 0)),
3302-
(i64 (EXTRACT_SUBREG ZPR:$Zs, dsub))>;
3303-
def : Pat<(vector_extract (nxv8f16 ZPR:$Zs), (i64 0)),
3304-
(f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3305-
def : Pat<(vector_extract (nxv4f16 ZPR:$Zs), (i64 0)),
3306-
(f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3307-
def : Pat<(vector_extract (nxv2f16 ZPR:$Zs), (i64 0)),
3308-
(f16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3309-
def : Pat<(vector_extract (nxv8bf16 ZPR:$Zs), (i64 0)),
3310-
(bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3311-
def : Pat<(vector_extract (nxv4bf16 ZPR:$Zs), (i64 0)),
3312-
(bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3313-
def : Pat<(vector_extract (nxv2bf16 ZPR:$Zs), (i64 0)),
3314-
(bf16 (EXTRACT_SUBREG ZPR:$Zs, hsub))>;
3315-
def : Pat<(vector_extract (nxv4f32 ZPR:$Zs), (i64 0)),
3316-
(f32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
3317-
def : Pat<(vector_extract (nxv2f32 ZPR:$Zs), (i64 0)),
3318-
(f32 (EXTRACT_SUBREG ZPR:$Zs, ssub))>;
3319-
def : Pat<(vector_extract (nxv2f64 ZPR:$Zs), (i64 0)),
3320-
(f64 (EXTRACT_SUBREG ZPR:$Zs, dsub))>;
3291+
def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$Zs), (i64 0))),
3292+
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
3293+
def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$Zs), (i64 0))),
3294+
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
3295+
def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$Zs), (i64 0))),
3296+
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
3297+
def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$Zs), (i64 0))),
3298+
(EXTRACT_SUBREG ZPR:$Zs, dsub)>;
3299+
def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$Zs), (i64 0))),
3300+
(EXTRACT_SUBREG ZPR:$Zs, hsub)>;
3301+
def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$Zs), (i64 0))),
3302+
(EXTRACT_SUBREG ZPR:$Zs, hsub)>;
3303+
def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$Zs), (i64 0))),
3304+
(EXTRACT_SUBREG ZPR:$Zs, hsub)>;
3305+
def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$Zs), (i64 0))),
3306+
(EXTRACT_SUBREG ZPR:$Zs, hsub)>;
3307+
def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$Zs), (i64 0))),
3308+
(EXTRACT_SUBREG ZPR:$Zs, hsub)>;
3309+
def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$Zs), (i64 0))),
3310+
(EXTRACT_SUBREG ZPR:$Zs, hsub)>;
3311+
def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$Zs), (i64 0))),
3312+
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
3313+
def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$Zs), (i64 0))),
3314+
(EXTRACT_SUBREG ZPR:$Zs, ssub)>;
3315+
def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$Zs), (i64 0))),
3316+
(EXTRACT_SUBREG ZPR:$Zs, dsub)>;
33213317
}
33223318

33233319
multiclass sve_predicated_add<SDNode extend, int value> {

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -958,39 +958,39 @@ multiclass sve_int_count_r_x64<bits<5> opc, string asm,
958958

959959
// combine_op(x, trunc(cntp(all_active, p))) ==> inst p, x
960960
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv16i1 (SVEAllActive)), (nxv16i1 PPRAny:$pred))))),
961-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
962-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
963-
sub_32))>;
961+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
962+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
963+
sub_32)>;
964964
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv8i1 (SVEAllActive)), (nxv8i1 PPRAny:$pred))))),
965-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
966-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
967-
sub_32))>;
965+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
966+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
967+
sub_32)>;
968968
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv4i1 (SVEAllActive)), (nxv4i1 PPRAny:$pred))))),
969-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
970-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
971-
sub_32))>;
969+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
970+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
971+
sub_32)>;
972972
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv2i1 (SVEAllActive)), (nxv2i1 PPRAny:$pred))))),
973-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
974-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
975-
sub_32))>;
973+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
974+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
975+
sub_32)>;
976976

977977
// combine_op(x, trunc(cntp(p, p))) ==> inst p, x
978978
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv16i1 PPRAny:$pred), (nxv16i1 PPRAny:$pred))))),
979-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
980-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
981-
sub_32))>;
979+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _B) PPRAny:$pred,
980+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
981+
sub_32)>;
982982
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv8i1 PPRAny:$pred), (nxv8i1 PPRAny:$pred))))),
983-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
984-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
985-
sub_32))>;
983+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _H) PPRAny:$pred,
984+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
985+
sub_32)>;
986986
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv4i1 PPRAny:$pred), (nxv4i1 PPRAny:$pred))))),
987-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
988-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
989-
sub_32))>;
987+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _S) PPRAny:$pred,
988+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
989+
sub_32)>;
990990
def : Pat<(i32 (combine_op GPR32:$Rn, (trunc (int_aarch64_sve_cntp_oneuse (nxv2i1 PPRAny:$pred), (nxv2i1 PPRAny:$pred))))),
991-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
992-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32)),
993-
sub_32))>;
991+
(EXTRACT_SUBREG (!cast<Instruction>(NAME # _D) PPRAny:$pred,
992+
(INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Rn, sub_32)),
993+
sub_32)>;
994994
}
995995

996996
class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
@@ -1195,19 +1195,19 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm,
11951195
(!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, $imm)>;
11961196

11971197
def : Pat<(i32 (op GPR32:$Rdn, (i32 (trunc (opcnt (sve_pred_enum:$pattern)))))),
1198-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1198+
(EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF),
11991199
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, 1),
1200-
sub_32))>;
1200+
sub_32)>;
12011201

12021202
def : Pat<(i32 (op GPR32:$Rdn, (mul (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (sve_cnt_mul_imm_i32 i32:$imm)))),
1203-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1203+
(EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF),
12041204
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
1205-
sub_32))>;
1205+
sub_32)>;
12061206

12071207
def : Pat<(i32 (op GPR32:$Rdn, (shl (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (sve_cnt_shl_imm i32:$imm)))),
1208-
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1208+
(EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (IMPLICIT_DEF),
12091209
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
1210-
sub_32))>;
1210+
sub_32)>;
12111211
}
12121212
}
12131213

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