@@ -21360,22 +21360,12 @@ static SDValue LowerVectorAllZero(const SDLoc &DL, SDValue V, ISD::CondCode CC,
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SelectionDAG &DAG, X86::CondCode &X86CC) {
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EVT VT = V.getValueType();
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- assert((CC == ISD::SETEQ || CC == ISD::SETNE) && "Unsupported ISD::CondCode");
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- X86CC = (CC == ISD::SETEQ ? X86::COND_E : X86::COND_NE);
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-
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- // For sub-128-bit vector, cast to (legal) integer and compare with zero.
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- if (VT.getSizeInBits() < 128) {
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- EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
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- if (!DAG.getTargetLoweringInfo().isTypeLegal(IntVT))
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- return SDValue();
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- return DAG.getNode(X86ISD::CMP, DL, MVT::i32, DAG.getBitcast(IntVT, V),
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- DAG.getConstant(0, DL, IntVT));
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- }
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-
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- // Quit if not splittable to 128/256-bit vector.
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- if (!isPowerOf2_32(VT.getSizeInBits()))
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+ // Quit if less than 128-bits or not splittable to 128/256-bit vector.
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+ if (VT.getSizeInBits() < 128 || !isPowerOf2_32(VT.getSizeInBits()))
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return SDValue();
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+ X86CC = (CC == ISD::SETEQ ? X86::COND_E : X86::COND_NE);
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+
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// Split down to 128/256-bit vector.
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unsigned TestSize = Subtarget.hasAVX() ? 256 : 128;
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while (VT.getSizeInBits() > TestSize) {
@@ -21399,19 +21389,18 @@ static SDValue LowerVectorAllZero(const SDLoc &DL, SDValue V, ISD::CondCode CC,
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DAG.getConstant(0xFFFF, DL, MVT::i32));
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}
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- // Check whether an OR'd reduction tree is PTEST-able, or if we can fallback to
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+ // Check whether an OR'd tree is PTEST-able, or if we can fallback to
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// CMP(MOVMSK(PCMPEQB(X,0))).
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static SDValue MatchVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
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- const SDLoc &DL,
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const X86Subtarget &Subtarget,
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SelectionDAG &DAG, SDValue &X86CC) {
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- assert((CC == ISD::SETEQ || CC == ISD::SETNE) && "Unsupported ISD::CondCode ");
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+ assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree. ");
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if (!Subtarget.hasSSE2() || !Op->hasOneUse())
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return SDValue();
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SmallVector<SDValue, 8> VecIns;
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- if (Op.getOpcode() == ISD::OR && matchScalarReduction(Op, ISD::OR, VecIns)) {
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+ if (matchScalarReduction(Op, ISD::OR, VecIns)) {
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EVT VT = VecIns[0].getValueType();
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assert(llvm::all_of(VecIns,
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[VT](SDValue V) { return VT == V.getValueType(); }) &&
@@ -21421,6 +21410,8 @@ static SDValue MatchVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
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if (VT.getSizeInBits() < 128 || !isPowerOf2_32(VT.getSizeInBits()))
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return SDValue();
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+ SDLoc DL(Op);
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+
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// If more than one full vector is evaluated, OR them first before PTEST.
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for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1;
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Slot += 2, e += 1) {
@@ -21439,19 +21430,6 @@ static SDValue MatchVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
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}
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}
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- if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
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- ISD::NodeType BinOp;
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- if (SDValue Match =
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- DAG.matchBinOpReduction(Op.getNode(), BinOp, {ISD::OR})) {
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- X86::CondCode CCode;
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- if (SDValue V =
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- LowerVectorAllZero(DL, Match, CC, Subtarget, DAG, CCode)) {
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- X86CC = DAG.getTargetConstant(CCode, DL, MVT::i8);
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- return V;
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- }
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- }
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- }
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-
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return SDValue();
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}
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@@ -22602,10 +22580,11 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
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// Try to use PTEST/PMOVMSKB for a tree ORs equality compared with 0.
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// TODO: We could do AND tree with all 1s as well by using the C flag.
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- if (isNullConstant(Op1) && (CC == ISD::SETEQ || CC == ISD::SETNE))
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- if (SDValue CmpZ =
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- MatchVectorAllZeroTest(Op0, CC, dl , Subtarget, DAG, X86CC))
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+ if (Op0.getOpcode() == ISD::OR && isNullConstant(Op1) &&
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+ (CC == ISD::SETEQ || CC == ISD::SETNE)) {
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+ if (SDValue CmpZ = MatchVectorAllZeroTest(Op0, CC, Subtarget, DAG, X86CC))
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return CmpZ;
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+ }
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// Try to lower using KORTEST or KTEST.
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if (SDValue Test = EmitAVX512Test(Op0, Op1, CC, dl, DAG, Subtarget, X86CC))
@@ -46085,14 +46064,6 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
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if (CC == ISD::SETNE || CC == ISD::SETEQ) {
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if (SDValue V = combineVectorSizedSetCCEquality(N, DAG, Subtarget))
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return V;
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-
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- if (VT == MVT::i1) {
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- SDValue X86CC;
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- if (SDValue V =
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- MatchVectorAllZeroTest(LHS, CC, DL, Subtarget, DAG, X86CC))
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- return DAG.getNode(ISD::TRUNCATE, DL, VT,
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- DAG.getNode(X86ISD::SETCC, DL, MVT::i8, X86CC, V));
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- }
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}
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
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