Skip to content

Commit 187f627

Browse files
SamTebbs33SamTebbs33
committed
[ARM] Allow tail predication on sadd_sat and uadd_sat intrinsics
This patch stops the sadd_sat and uadd_sat intrinsics from blocking tail predication. Differential revision: https://reviews.llvm.org/D82377
1 parent 22f02db commit 187f627

File tree

2 files changed

+117
-2
lines changed

2 files changed

+117
-2
lines changed

‎llvm/lib/Target/ARM/MVETailPredication.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -354,8 +354,14 @@ bool MVETailPredication::IsPredicatedVectorLoop() {
354354
return false;
355355
MaskedInsts.push_back(cast<IntrinsicInst>(&I));
356356
} else if (auto *Int = dyn_cast<IntrinsicInst>(&I)) {
357-
if (Int->getIntrinsicID() == Intrinsic::fma)
358-
continue;
357+
switch (Int->getIntrinsicID()) {
358+
case Intrinsic::fma:
359+
case Intrinsic::sadd_sat:
360+
case Intrinsic::uadd_sat:
361+
continue;
362+
default:
363+
break;
364+
}
359365
for (auto &U : Int->args()) {
360366
if (isa<VectorType>(U->getType()))
361367
return false;

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-add-sat.ll

Lines changed: 109 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,109 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs -disable-mve-tail-predication=false -o - %s | FileCheck %s
3+
define arm_aapcs_vfpcc void @uadd_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
4+
; CHECK-LABEL: uadd_sat:
5+
; CHECK: @ %bb.0: @ %entry
6+
; CHECK-NEXT: .save {r7, lr}
7+
; CHECK-NEXT: push {r7, lr}
8+
; CHECK-NEXT: cmp r3, #0
9+
; CHECK-NEXT: it eq
10+
; CHECK-NEXT: popeq {r7, pc}
11+
; CHECK-NEXT: dlstp.16 lr, r3
12+
; CHECK-NEXT: .LBB0_1: @ %vector.body
13+
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
14+
; CHECK-NEXT: vldrh.u16 q0, [r1], #16
15+
; CHECK-NEXT: vldrh.u16 q1, [r0], #16
16+
; CHECK-NEXT: vqadd.u16 q0, q1, q0
17+
; CHECK-NEXT: vstrh.16 q0, [r2], #16
18+
; CHECK-NEXT: letp lr, .LBB0_1
19+
; CHECK-NEXT: @ %bb.2: @ %while.end
20+
; CHECK-NEXT: pop {r7, pc}
21+
entry:
22+
%cmp7 = icmp eq i32 %blockSize, 0
23+
br i1 %cmp7, label %while.end, label %vector.ph
24+
25+
vector.ph: ; preds = %entry
26+
%n.rnd.up = add i32 %blockSize, 7
27+
%n.vec = and i32 %n.rnd.up, -8
28+
%trip.count.minus.1 = add i32 %blockSize, -1
29+
br label %vector.body
30+
31+
vector.body: ; preds = %vector.body, %vector.ph
32+
%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
33+
%next.gep = getelementptr i16, i16* %pSrcA, i32 %index
34+
%next.gep20 = getelementptr i16, i16* %pDst, i32 %index
35+
%next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index
36+
%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %trip.count.minus.1)
37+
%0 = bitcast i16* %next.gep to <8 x i16>*
38+
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
39+
%1 = bitcast i16* %next.gep21 to <8 x i16>*
40+
%wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
41+
%2 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24)
42+
%3 = bitcast i16* %next.gep20 to <8 x i16>*
43+
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
44+
%index.next = add i32 %index, 8
45+
%4 = icmp eq i32 %index.next, %n.vec
46+
br i1 %4, label %while.end, label %vector.body
47+
48+
while.end: ; preds = %vector.body, %entry
49+
ret void
50+
}
51+
52+
define arm_aapcs_vfpcc void @sadd_sat(i16* noalias nocapture readonly %pSrcA, i16* noalias nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %blockSize) {
53+
; CHECK-LABEL: sadd_sat:
54+
; CHECK: @ %bb.0: @ %entry
55+
; CHECK-NEXT: .save {r7, lr}
56+
; CHECK-NEXT: push {r7, lr}
57+
; CHECK-NEXT: cmp r3, #0
58+
; CHECK-NEXT: it eq
59+
; CHECK-NEXT: popeq {r7, pc}
60+
; CHECK-NEXT: dlstp.16 lr, r3
61+
; CHECK-NEXT: .LBB1_1: @ %vector.body
62+
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
63+
; CHECK-NEXT: vldrh.u16 q0, [r1], #16
64+
; CHECK-NEXT: vldrh.u16 q1, [r0], #16
65+
; CHECK-NEXT: vqadd.s16 q0, q1, q0
66+
; CHECK-NEXT: vstrh.16 q0, [r2], #16
67+
; CHECK-NEXT: letp lr, .LBB1_1
68+
; CHECK-NEXT: @ %bb.2: @ %while.end
69+
; CHECK-NEXT: pop {r7, pc}
70+
entry:
71+
%cmp7 = icmp eq i32 %blockSize, 0
72+
br i1 %cmp7, label %while.end, label %vector.ph
73+
74+
vector.ph: ; preds = %entry
75+
%n.rnd.up = add i32 %blockSize, 7
76+
%n.vec = and i32 %n.rnd.up, -8
77+
%trip.count.minus.1 = add i32 %blockSize, -1
78+
br label %vector.body
79+
80+
vector.body: ; preds = %vector.body, %vector.ph
81+
%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
82+
%next.gep = getelementptr i16, i16* %pSrcA, i32 %index
83+
%next.gep20 = getelementptr i16, i16* %pDst, i32 %index
84+
%next.gep21 = getelementptr i16, i16* %pSrcB, i32 %index
85+
%active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %trip.count.minus.1)
86+
%0 = bitcast i16* %next.gep to <8 x i16>*
87+
%wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %0, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
88+
%1 = bitcast i16* %next.gep21 to <8 x i16>*
89+
%wide.masked.load24 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %1, i32 2, <8 x i1> %active.lane.mask, <8 x i16> undef)
90+
%2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %wide.masked.load, <8 x i16> %wide.masked.load24)
91+
%3 = bitcast i16* %next.gep20 to <8 x i16>*
92+
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %2, <8 x i16>* %3, i32 2, <8 x i1> %active.lane.mask)
93+
%index.next = add i32 %index, 8
94+
%4 = icmp eq i32 %index.next, %n.vec
95+
br i1 %4, label %while.end, label %vector.body
96+
97+
while.end: ; preds = %vector.body, %entry
98+
ret void
99+
}
100+
101+
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
102+
103+
declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
104+
105+
declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
106+
107+
declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
108+
109+
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)

0 commit comments

Comments
 (0)