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[ARM] Patterns for VQSHRN
Given a VQMOVN(VSHR), we can fold that into a VQSHRN simply enough using a few tablegen patterns. Differential Revision: https://reviews.llvm.org/D77720
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-68
lines changed

3 files changed

+52
-68
lines changed

‎llvm/lib/Target/ARM/ARMInstrMVE.td

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4737,6 +4737,24 @@ let Predicates = [HasMVEInt] in {
47374737
(v16i8 (MVE_VQMOVNu16bh (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
47384738
def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 1))),
47394739
(v16i8 (MVE_VQMOVNu16th (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
4740+
4741+
def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
4742+
(v8i16 (MVE_VQSHRNbhs32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4743+
def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
4744+
(v16i8 (MVE_VQSHRNbhs16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
4745+
def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
4746+
(v8i16 (MVE_VQSHRNths32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4747+
def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
4748+
(v16i8 (MVE_VQSHRNths16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
4749+
4750+
def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
4751+
(v8i16 (MVE_VQSHRNbhu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4752+
def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
4753+
(v16i8 (MVE_VQSHRNbhu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
4754+
def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
4755+
(v8i16 (MVE_VQSHRNthu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4756+
def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
4757+
(v16i8 (MVE_VQSHRNthu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
47404758
}
47414759

47424760
class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,

‎llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

Lines changed: 26 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1135,8 +1135,7 @@ define arm_aapcs_vfpcc void @ssatmul_4_q15(i16* nocapture readonly %pSrcA, i16*
11351135
; CHECK-NEXT: vldrh.s32 q0, [r0], #8
11361136
; CHECK-NEXT: vldrh.s32 q1, [r1], #8
11371137
; CHECK-NEXT: vmul.i32 q0, q1, q0
1138-
; CHECK-NEXT: vshr.s32 q0, q0, #15
1139-
; CHECK-NEXT: vqmovnb.s32 q0, q0
1138+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
11401139
; CHECK-NEXT: vstrh.32 q0, [r2], #8
11411140
; CHECK-NEXT: le lr, .LBB5_4
11421141
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -1274,13 +1273,11 @@ define arm_aapcs_vfpcc void @ssatmul_8_q15(i16* nocapture readonly %pSrcA, i16*
12741273
; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
12751274
; CHECK-NEXT: vmul.i32 q0, q1, q0
12761275
; CHECK-NEXT: vldrh.s32 q1, [r1], #16
1277-
; CHECK-NEXT: vshr.s32 q0, q0, #15
1278-
; CHECK-NEXT: vqmovnb.s32 q0, q0
1276+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
12791277
; CHECK-NEXT: vstrh.32 q0, [r2, #8]
12801278
; CHECK-NEXT: vldrh.s32 q0, [r0], #16
12811279
; CHECK-NEXT: vmul.i32 q0, q1, q0
1282-
; CHECK-NEXT: vshr.s32 q0, q0, #15
1283-
; CHECK-NEXT: vqmovnb.s32 q0, q0
1280+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
12841281
; CHECK-NEXT: vstrh.32 q0, [r2], #16
12851282
; CHECK-NEXT: le lr, .LBB6_4
12861283
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -1418,11 +1415,9 @@ define arm_aapcs_vfpcc void @ssatmul_8i_q15(i16* nocapture readonly %pSrcA, i16*
14181415
; CHECK-NEXT: vldrh.u16 q1, [r1], #16
14191416
; CHECK-NEXT: vmullt.s16 q2, q1, q0
14201417
; CHECK-NEXT: vmullb.s16 q0, q1, q0
1421-
; CHECK-NEXT: vshr.s32 q0, q0, #15
1422-
; CHECK-NEXT: vshr.s32 q2, q2, #15
1423-
; CHECK-NEXT: vqmovnb.s32 q0, q0
1418+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
14241419
; CHECK-NEXT: vmovlb.s16 q0, q0
1425-
; CHECK-NEXT: vqmovnt.s32 q0, q2
1420+
; CHECK-NEXT: vqshrnt.s32 q0, q2, #15
14261421
; CHECK-NEXT: vstrb.8 q0, [r2], #16
14271422
; CHECK-NEXT: le lr, .LBB7_4
14281423
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -1570,8 +1565,7 @@ define arm_aapcs_vfpcc void @ssatmul_s4t_q15(i16* nocapture readonly %pSrcA, i16
15701565
; CHECK-NEXT: vldrht.s32 q2, [r0], #8
15711566
; CHECK-NEXT: vldrht.s32 q3, [r1], #8
15721567
; CHECK-NEXT: vmul.i32 q2, q3, q2
1573-
; CHECK-NEXT: vshr.s32 q2, q2, #15
1574-
; CHECK-NEXT: vqmovnb.s32 q2, q2
1568+
; CHECK-NEXT: vqshrnb.s32 q2, q2, #15
15751569
; CHECK-NEXT: vmovlb.s16 q2, q2
15761570
; CHECK-NEXT: vpst
15771571
; CHECK-NEXT: vstrht.32 q2, [r2], #8
@@ -1705,8 +1699,7 @@ define arm_aapcs_vfpcc void @ssatmul_8t_q15(i16* nocapture readonly %pSrcA, i16*
17051699
; CHECK-NEXT: vmov.u16 r4, q7[3]
17061700
; CHECK-NEXT: vmov.32 q0[3], r4
17071701
; CHECK-NEXT: vmullb.s16 q0, q0, q5
1708-
; CHECK-NEXT: vshr.s32 q0, q0, #15
1709-
; CHECK-NEXT: vqmovnb.s32 q0, q0
1702+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
17101703
; CHECK-NEXT: vmovlb.s16 q0, q0
17111704
; CHECK-NEXT: vmov r4, s0
17121705
; CHECK-NEXT: vmov.16 q5[0], r4
@@ -1733,8 +1726,7 @@ define arm_aapcs_vfpcc void @ssatmul_8t_q15(i16* nocapture readonly %pSrcA, i16*
17331726
; CHECK-NEXT: vmov.u16 r4, q7[7]
17341727
; CHECK-NEXT: vmov.32 q6[3], r4
17351728
; CHECK-NEXT: vmullb.s16 q0, q6, q0
1736-
; CHECK-NEXT: vshr.s32 q0, q0, #15
1737-
; CHECK-NEXT: vqmovnb.s32 q0, q0
1729+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
17381730
; CHECK-NEXT: vmovlb.s16 q0, q0
17391731
; CHECK-NEXT: vmov r4, s0
17401732
; CHECK-NEXT: vmov.16 q5[4], r4
@@ -1863,11 +1855,9 @@ define arm_aapcs_vfpcc void @ssatmul_8ti_q15(i16* nocapture readonly %pSrcA, i16
18631855
; CHECK-NEXT: vldrht.u16 q6, [r1], #16
18641856
; CHECK-NEXT: vmullt.s16 q7, q6, q5
18651857
; CHECK-NEXT: vmullb.s16 q5, q6, q5
1866-
; CHECK-NEXT: vshr.s32 q7, q7, #15
1867-
; CHECK-NEXT: vshr.s32 q5, q5, #15
1868-
; CHECK-NEXT: vqmovnb.s32 q5, q5
1858+
; CHECK-NEXT: vqshrnb.s32 q5, q5, #15
18691859
; CHECK-NEXT: vmovlb.s16 q5, q5
1870-
; CHECK-NEXT: vqmovnt.s32 q5, q7
1860+
; CHECK-NEXT: vqshrnt.s32 q5, q7, #15
18711861
; CHECK-NEXT: vpst
18721862
; CHECK-NEXT: vstrht.16 q5, [r2], #16
18731863
; CHECK-NEXT: le lr, .LBB10_2
@@ -1973,8 +1963,7 @@ define arm_aapcs_vfpcc void @usatmul_4_q15(i16* nocapture readonly %pSrcA, i16*
19731963
; CHECK-NEXT: vldrh.u32 q0, [r0], #8
19741964
; CHECK-NEXT: vldrh.u32 q1, [r1], #8
19751965
; CHECK-NEXT: vmul.i32 q0, q1, q0
1976-
; CHECK-NEXT: vshr.u32 q0, q0, #15
1977-
; CHECK-NEXT: vqmovnb.u32 q0, q0
1966+
; CHECK-NEXT: vqshrnb.u32 q0, q0, #15
19781967
; CHECK-NEXT: vstrh.32 q0, [r2], #8
19791968
; CHECK-NEXT: le lr, .LBB11_4
19801969
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -2104,13 +2093,11 @@ define arm_aapcs_vfpcc void @usatmul_8_q15(i16* nocapture readonly %pSrcA, i16*
21042093
; CHECK-NEXT: vldrh.u32 q1, [r1, #8]
21052094
; CHECK-NEXT: vmul.i32 q0, q1, q0
21062095
; CHECK-NEXT: vldrh.u32 q1, [r1], #16
2107-
; CHECK-NEXT: vshr.u32 q0, q0, #15
2108-
; CHECK-NEXT: vqmovnb.u32 q0, q0
2096+
; CHECK-NEXT: vqshrnb.u32 q0, q0, #15
21092097
; CHECK-NEXT: vstrh.32 q0, [r2, #8]
21102098
; CHECK-NEXT: vldrh.u32 q0, [r0], #16
21112099
; CHECK-NEXT: vmul.i32 q0, q1, q0
2112-
; CHECK-NEXT: vshr.u32 q0, q0, #15
2113-
; CHECK-NEXT: vqmovnb.u32 q0, q0
2100+
; CHECK-NEXT: vqshrnb.u32 q0, q0, #15
21142101
; CHECK-NEXT: vstrh.32 q0, [r2], #16
21152102
; CHECK-NEXT: le lr, .LBB12_4
21162103
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -2381,8 +2368,7 @@ define arm_aapcs_vfpcc void @ssatmul_8_q7(i8* nocapture readonly %pSrcA, i8* noc
23812368
; CHECK-NEXT: vldrb.s16 q0, [r0], #8
23822369
; CHECK-NEXT: vldrb.s16 q1, [r1], #8
23832370
; CHECK-NEXT: vmul.i16 q0, q1, q0
2384-
; CHECK-NEXT: vshr.s16 q0, q0, #7
2385-
; CHECK-NEXT: vqmovnb.s16 q0, q0
2371+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
23862372
; CHECK-NEXT: vstrb.16 q0, [r2], #8
23872373
; CHECK-NEXT: le lr, .LBB14_4
23882374
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -2518,13 +2504,11 @@ define arm_aapcs_vfpcc void @ssatmul_16_q7(i8* nocapture readonly %pSrcA, i8* no
25182504
; CHECK-NEXT: vldrb.s16 q1, [r1, #8]
25192505
; CHECK-NEXT: vmul.i16 q0, q1, q0
25202506
; CHECK-NEXT: vldrb.s16 q1, [r1], #16
2521-
; CHECK-NEXT: vshr.s16 q0, q0, #7
2522-
; CHECK-NEXT: vqmovnb.s16 q0, q0
2507+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
25232508
; CHECK-NEXT: vstrb.16 q0, [r2, #8]
25242509
; CHECK-NEXT: vldrb.s16 q0, [r0], #16
25252510
; CHECK-NEXT: vmul.i16 q0, q1, q0
2526-
; CHECK-NEXT: vshr.s16 q0, q0, #7
2527-
; CHECK-NEXT: vqmovnb.s16 q0, q0
2511+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
25282512
; CHECK-NEXT: vstrb.16 q0, [r2], #16
25292513
; CHECK-NEXT: le lr, .LBB15_4
25302514
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -2660,11 +2644,9 @@ define arm_aapcs_vfpcc void @ssatmul_16i_q7(i8* nocapture readonly %pSrcA, i8* n
26602644
; CHECK-NEXT: vldrb.u8 q1, [r1], #16
26612645
; CHECK-NEXT: vmullt.s8 q2, q1, q0
26622646
; CHECK-NEXT: vmullb.s8 q0, q1, q0
2663-
; CHECK-NEXT: vshr.s16 q0, q0, #7
2664-
; CHECK-NEXT: vshr.s16 q2, q2, #7
2665-
; CHECK-NEXT: vqmovnb.s16 q0, q0
2647+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
26662648
; CHECK-NEXT: vmovlb.s8 q0, q0
2667-
; CHECK-NEXT: vqmovnt.s16 q0, q2
2649+
; CHECK-NEXT: vqshrnt.s16 q0, q2, #7
26682650
; CHECK-NEXT: vstrb.8 q0, [r2], #16
26692651
; CHECK-NEXT: le lr, .LBB16_4
26702652
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -2837,8 +2819,7 @@ define arm_aapcs_vfpcc void @ssatmul_8t_q7(i8* nocapture readonly %pSrcA, i8* no
28372819
; CHECK-NEXT: vldrbt.s16 q5, [r0], #8
28382820
; CHECK-NEXT: vldrbt.s16 q6, [r1], #8
28392821
; CHECK-NEXT: vmul.i16 q5, q6, q5
2840-
; CHECK-NEXT: vshr.s16 q5, q5, #7
2841-
; CHECK-NEXT: vqmovnb.s16 q5, q5
2822+
; CHECK-NEXT: vqshrnb.s16 q5, q5, #7
28422823
; CHECK-NEXT: vmovlb.s8 q5, q5
28432824
; CHECK-NEXT: vpst
28442825
; CHECK-NEXT: vstrbt.16 q5, [r2], #8
@@ -3060,8 +3041,7 @@ define arm_aapcs_vfpcc void @ssatmul_16t_q7(i8* nocapture readonly %pSrcA, i8* n
30603041
; CHECK-NEXT: vmov.u8 r4, q4[7]
30613042
; CHECK-NEXT: vmov.16 q5[7], r4
30623043
; CHECK-NEXT: vmullb.s8 q5, q5, q7
3063-
; CHECK-NEXT: vshr.s16 q5, q5, #7
3064-
; CHECK-NEXT: vqmovnb.s16 q5, q5
3044+
; CHECK-NEXT: vqshrnb.s16 q5, q5, #7
30653045
; CHECK-NEXT: vmovlb.s8 q5, q5
30663046
; CHECK-NEXT: vmov.u16 r4, q5[0]
30673047
; CHECK-NEXT: vmov.8 q7[0], r4
@@ -3112,8 +3092,7 @@ define arm_aapcs_vfpcc void @ssatmul_16t_q7(i8* nocapture readonly %pSrcA, i8* n
31123092
; CHECK-NEXT: vmov.u8 r4, q4[15]
31133093
; CHECK-NEXT: vmov.16 q0[7], r4
31143094
; CHECK-NEXT: vmullb.s8 q0, q0, q5
3115-
; CHECK-NEXT: vshr.s16 q0, q0, #7
3116-
; CHECK-NEXT: vqmovnb.s16 q0, q0
3095+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
31173096
; CHECK-NEXT: vmovlb.s8 q0, q0
31183097
; CHECK-NEXT: vmov.u16 r4, q0[0]
31193098
; CHECK-NEXT: vmov.8 q7[8], r4
@@ -3330,11 +3309,9 @@ define arm_aapcs_vfpcc void @ssatmul_16ti_q7(i8* nocapture readonly %pSrcA, i8*
33303309
; CHECK-NEXT: vldrbt.u8 q4, [r1], #16
33313310
; CHECK-NEXT: vmullt.s8 q5, q4, q0
33323311
; CHECK-NEXT: vmullb.s8 q0, q4, q0
3333-
; CHECK-NEXT: vshr.s16 q0, q0, #7
3334-
; CHECK-NEXT: vshr.s16 q5, q5, #7
3335-
; CHECK-NEXT: vqmovnb.s16 q0, q0
3312+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
33363313
; CHECK-NEXT: vmovlb.s8 q0, q0
3337-
; CHECK-NEXT: vqmovnt.s16 q0, q5
3314+
; CHECK-NEXT: vqshrnt.s16 q0, q5, #7
33383315
; CHECK-NEXT: vpst
33393316
; CHECK-NEXT: vstrbt.8 q0, [r2], #16
33403317
; CHECK-NEXT: le lr, .LBB19_2
@@ -3451,8 +3428,7 @@ define arm_aapcs_vfpcc void @usatmul_8_q7(i8* nocapture readonly %pSrcA, i8* noc
34513428
; CHECK-NEXT: vldrb.u16 q0, [r0], #8
34523429
; CHECK-NEXT: vldrb.u16 q1, [r1], #8
34533430
; CHECK-NEXT: vmul.i16 q0, q1, q0
3454-
; CHECK-NEXT: vshr.u16 q0, q0, #7
3455-
; CHECK-NEXT: vqmovnb.u16 q0, q0
3431+
; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
34563432
; CHECK-NEXT: vstrb.16 q0, [r2], #8
34573433
; CHECK-NEXT: le lr, .LBB20_4
34583434
; CHECK-NEXT: @ %bb.5: @ %middle.block
@@ -3581,14 +3557,12 @@ define arm_aapcs_vfpcc void @usatmul_16_q7(i8* nocapture readonly %pSrcA, i8* no
35813557
; CHECK-NEXT: vldrb.u16 q1, [r1, #8]
35823558
; CHECK-NEXT: vmul.i16 q0, q1, q0
35833559
; CHECK-NEXT: vldrb.u16 q1, [r1], #16
3584-
; CHECK-NEXT: vshr.u16 q0, q0, #7
3585-
; CHECK-NEXT: vqmovnb.u16 q0, q0
3560+
; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
35863561
; CHECK-NEXT: vmovlb.u8 q0, q0
35873562
; CHECK-NEXT: vstrb.16 q0, [r2, #8]
35883563
; CHECK-NEXT: vldrb.u16 q0, [r0], #16
35893564
; CHECK-NEXT: vmul.i16 q0, q1, q0
3590-
; CHECK-NEXT: vshr.u16 q0, q0, #7
3591-
; CHECK-NEXT: vqmovnb.u16 q0, q0
3565+
; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
35923566
; CHECK-NEXT: vmovlb.u8 q0, q0
35933567
; CHECK-NEXT: vstrb.16 q0, [r2], #16
35943568
; CHECK-NEXT: le lr, .LBB21_4

‎llvm/test/CodeGen/Thumb2/mve-vqshrn.ll

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,7 @@
44
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_smaxmin(<4 x i32> %so) {
55
; CHECK-LABEL: vqshrni32_smaxmin:
66
; CHECK: @ %bb.0: @ %entry
7-
; CHECK-NEXT: vshr.s32 q0, q0, #3
8-
; CHECK-NEXT: vqmovnb.s32 q0, q0
7+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #3
98
; CHECK-NEXT: vmovlb.s16 q0, q0
109
; CHECK-NEXT: bx lr
1110
entry:
@@ -20,8 +19,7 @@ entry:
2019
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_sminmax(<4 x i32> %so) {
2120
; CHECK-LABEL: vqshrni32_sminmax:
2221
; CHECK: @ %bb.0: @ %entry
23-
; CHECK-NEXT: vshr.s32 q0, q0, #3
24-
; CHECK-NEXT: vqmovnb.s32 q0, q0
22+
; CHECK-NEXT: vqshrnb.s32 q0, q0, #3
2523
; CHECK-NEXT: vmovlb.s16 q0, q0
2624
; CHECK-NEXT: bx lr
2725
entry:
@@ -36,8 +34,7 @@ entry:
3634
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_umaxmin(<4 x i32> %so) {
3735
; CHECK-LABEL: vqshrni32_umaxmin:
3836
; CHECK: @ %bb.0: @ %entry
39-
; CHECK-NEXT: vshr.u32 q0, q0, #3
40-
; CHECK-NEXT: vqmovnb.u32 q0, q0
37+
; CHECK-NEXT: vqshrnb.u32 q0, q0, #3
4138
; CHECK-NEXT: vmovlb.u16 q0, q0
4239
; CHECK-NEXT: bx lr
4340
entry:
@@ -50,8 +47,7 @@ entry:
5047
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_uminmax(<4 x i32> %so) {
5148
; CHECK-LABEL: vqshrni32_uminmax:
5249
; CHECK: @ %bb.0: @ %entry
53-
; CHECK-NEXT: vshr.u32 q0, q0, #3
54-
; CHECK-NEXT: vqmovnb.u32 q0, q0
50+
; CHECK-NEXT: vqshrnb.u32 q0, q0, #3
5551
; CHECK-NEXT: vmovlb.u16 q0, q0
5652
; CHECK-NEXT: bx lr
5753
entry:
@@ -64,8 +60,7 @@ entry:
6460
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_smaxmin(<8 x i16> %so) {
6561
; CHECK-LABEL: vqshrni16_smaxmin:
6662
; CHECK: @ %bb.0: @ %entry
67-
; CHECK-NEXT: vshr.s16 q0, q0, #3
68-
; CHECK-NEXT: vqmovnb.s16 q0, q0
63+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #3
6964
; CHECK-NEXT: vmovlb.s8 q0, q0
7065
; CHECK-NEXT: bx lr
7166
entry:
@@ -80,8 +75,7 @@ entry:
8075
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_sminmax(<8 x i16> %so) {
8176
; CHECK-LABEL: vqshrni16_sminmax:
8277
; CHECK: @ %bb.0: @ %entry
83-
; CHECK-NEXT: vshr.s16 q0, q0, #3
84-
; CHECK-NEXT: vqmovnb.s16 q0, q0
78+
; CHECK-NEXT: vqshrnb.s16 q0, q0, #3
8579
; CHECK-NEXT: vmovlb.s8 q0, q0
8680
; CHECK-NEXT: bx lr
8781
entry:
@@ -96,8 +90,7 @@ entry:
9690
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_umaxmin(<8 x i16> %so) {
9791
; CHECK-LABEL: vqshrni16_umaxmin:
9892
; CHECK: @ %bb.0: @ %entry
99-
; CHECK-NEXT: vshr.u16 q0, q0, #3
100-
; CHECK-NEXT: vqmovnb.u16 q0, q0
93+
; CHECK-NEXT: vqshrnb.u16 q0, q0, #3
10194
; CHECK-NEXT: vmovlb.u8 q0, q0
10295
; CHECK-NEXT: bx lr
10396
entry:
@@ -110,8 +103,7 @@ entry:
110103
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_uminmax(<8 x i16> %so) {
111104
; CHECK-LABEL: vqshrni16_uminmax:
112105
; CHECK: @ %bb.0: @ %entry
113-
; CHECK-NEXT: vshr.u16 q0, q0, #3
114-
; CHECK-NEXT: vqmovnb.u16 q0, q0
106+
; CHECK-NEXT: vqshrnb.u16 q0, q0, #3
115107
; CHECK-NEXT: vmovlb.u8 q0, q0
116108
; CHECK-NEXT: bx lr
117109
entry:

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