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iclsrc
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Merge from 'sycl' to 'sycl-web'
2 parents e79b586 + 5947cde commit 2b6902c

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‎buildbot/dependency.conf

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@ ocl_cpu_rt_ver=2020.11.8.0.27
44
# https://github.com/intel/llvm/releases/download/2020-WW36/win-oclcpuexp-2020.11.8.0.27_rel.zip
55
ocl_cpu_rt_ver_win=2020.11.8.0.27
66
# Same GPU driver supports Level Zero and OpenCL:
7-
# https://github.com/intel/compute-runtime/releases/tag/20.37.17906
8-
ocl_gpu_rt_ver=20.37.17906
7+
# https://github.com/intel/compute-runtime/releases/tag/20.39.17972
8+
ocl_gpu_rt_ver=20.39.17972
99
# Same GPU driver supports Level Zero and OpenCL:
1010
# https://downloadmirror.intel.com/29879/a08/igfx_win10_100.8778.zip
1111
ocl_gpu_rt_ver_win=27.20.100.8778
@@ -24,7 +24,7 @@ fpga_ver_win=20200811_000006
2424
[DRIVER VERSIONS]
2525
cpu_driver_lin=2020.11.8.0.27
2626
cpu_driver_win=2020.11.8.0.27
27-
gpu_driver_lin=20.37.17906
27+
gpu_driver_lin=20.39.17972
2828
gpu_driver_win=27.20.100.8778
2929
fpga_driver_lin=2020.11.8.0.27
3030
fpga_driver_win=2020.11.8.0.27

‎clang/include/clang/Basic/Attr.td

Lines changed: 48 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1217,7 +1217,8 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
12171217
}
12181218

12191219
def SYCLIntelNumSimdWorkItems : InheritableAttr {
1220-
let Spellings = [CXX11<"intelfpga","num_simd_work_items">];
1220+
let Spellings = [CXX11<"intelfpga","num_simd_work_items">,
1221+
CXX11<"intel","num_simd_work_items">];
12211222
let Args = [ExprArgument<"Value">];
12221223
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12231224
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1226,7 +1227,8 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
12261227
}
12271228

12281229
def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
1229-
let Spellings = [CXX11<"intelfpga","scheduler_target_fmax_mhz">];
1230+
let Spellings = [CXX11<"intelfpga","scheduler_target_fmax_mhz">,
1231+
CXX11<"intel","scheduler_target_fmax_mhz">];
12301232
let Args = [ExprArgument<"Value">];
12311233
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12321234
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1244,7 +1246,8 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
12441246
}
12451247

12461248
def SYCLIntelMaxWorkGroupSize : InheritableAttr {
1247-
let Spellings = [CXX11<"intelfpga","max_work_group_size">];
1249+
let Spellings = [CXX11<"intelfpga","max_work_group_size">,
1250+
CXX11<"intel","max_work_group_size">];
12481251
let Args = [UnsignedArgument<"XDim">,
12491252
UnsignedArgument<"YDim">,
12501253
UnsignedArgument<"ZDim">];
@@ -1255,7 +1258,8 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
12551258
}
12561259

12571260
def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
1258-
let Spellings = [CXX11<"intelfpga","max_global_work_dim">];
1261+
let Spellings = [CXX11<"intelfpga","max_global_work_dim">,
1262+
CXX11<"intel","max_global_work_dim">];
12591263
let Args = [UnsignedArgument<"Number">];
12601264
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12611265
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1264,7 +1268,8 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
12641268
}
12651269

12661270
def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
1267-
let Spellings = [CXX11<"intelfpga","no_global_work_offset">];
1271+
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
1272+
CXX11<"intel","no_global_work_offset">];
12681273
let Args = [BoolArgument<"Enabled", 1>];
12691274
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12701275
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1717,7 +1722,8 @@ def Mode : Attr {
17171722
}
17181723

17191724
def SYCLIntelFPGAIVDep : Attr {
1720-
let Spellings = [CXX11<"intelfpga","ivdep">];
1725+
let Spellings = [CXX11<"intelfpga","ivdep">,
1726+
CXX11<"intel","ivdep">];
17211727
let Args = [
17221728
ExprArgument<"SafelenExpr">, ExprArgument<"ArrayExpr">,
17231729
UnsignedArgument<"SafelenValue">
@@ -1763,7 +1769,8 @@ def SYCLIntelFPGAIVDep : Attr {
17631769
}
17641770

17651771
def SYCLIntelFPGAII : Attr {
1766-
let Spellings = [CXX11<"intelfpga","ii">];
1772+
let Spellings = [CXX11<"intelfpga","ii">,
1773+
CXX11<"intel","ii">];
17671774
let Args = [ExprArgument<"IntervalExpr">];
17681775
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17691776
let HasCustomTypeTransform = 1;
@@ -1776,7 +1783,8 @@ def SYCLIntelFPGAII : Attr {
17761783
}
17771784

17781785
def SYCLIntelFPGAMaxConcurrency : Attr {
1779-
let Spellings = [CXX11<"intelfpga","max_concurrency">];
1786+
let Spellings = [CXX11<"intelfpga","max_concurrency">,
1787+
CXX11<"intel","max_concurrency">];
17801788
let Args = [ExprArgument<"NThreadsExpr">];
17811789
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17821790
let HasCustomTypeTransform = 1;
@@ -1789,7 +1797,8 @@ def SYCLIntelFPGAMaxConcurrency : Attr {
17891797
}
17901798

17911799
def SYCLIntelFPGALoopCoalesce : Attr {
1792-
let Spellings = [CXX11<"intelfpga","loop_coalesce">];
1800+
let Spellings = [CXX11<"intelfpga","loop_coalesce">,
1801+
CXX11<"intel","loop_coalesce">];
17931802
let Args = [ExprArgument<"NExpr">];
17941803
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17951804
let HasCustomTypeTransform = 1;
@@ -1802,7 +1811,8 @@ def SYCLIntelFPGALoopCoalesce : Attr {
18021811
}
18031812

18041813
def SYCLIntelFPGADisableLoopPipelining : Attr {
1805-
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">];
1814+
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">,
1815+
CXX11<"intel","disable_loop_pipelining">];
18061816
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18071817
let HasCustomTypeTransform = 1;
18081818
let AdditionalMembers = [{
@@ -1814,7 +1824,8 @@ def SYCLIntelFPGADisableLoopPipelining : Attr {
18141824
}
18151825

18161826
def SYCLIntelFPGAMaxInterleaving : Attr {
1817-
let Spellings = [CXX11<"intelfpga","max_interleaving">];
1827+
let Spellings = [CXX11<"intelfpga","max_interleaving">,
1828+
CXX11<"intel","max_interleaving">];
18181829
let Args = [ExprArgument<"NExpr">];
18191830
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18201831
let HasCustomTypeTransform = 1;
@@ -1827,7 +1838,8 @@ def SYCLIntelFPGAMaxInterleaving : Attr {
18271838
}
18281839

18291840
def SYCLIntelFPGASpeculatedIterations : Attr {
1830-
let Spellings = [CXX11<"intelfpga","speculated_iterations">];
1841+
let Spellings = [CXX11<"intelfpga","speculated_iterations">,
1842+
CXX11<"intel","speculated_iterations">];
18311843
let Args = [ExprArgument<"NExpr">];
18321844
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18331845
let HasCustomTypeTransform = 1;
@@ -1872,23 +1884,26 @@ def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
18721884
"local variables, static variables">;
18731885

18741886
def IntelFPGADoublePump : Attr {
1875-
let Spellings = [CXX11<"intelfpga", "doublepump">];
1887+
let Spellings = [CXX11<"intelfpga", "doublepump">,
1888+
CXX11<"intel", "doublepump">];
18761889
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
18771890
Field], ErrorDiag>;
18781891
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18791892
let Documentation = [IntelFPGADoublePumpAttrDocs];
18801893
}
18811894

18821895
def IntelFPGASinglePump : Attr {
1883-
let Spellings = [CXX11<"intelfpga", "singlepump">];
1896+
let Spellings = [CXX11<"intelfpga", "singlepump">,
1897+
CXX11<"intel", "singlepump">];
18841898
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
18851899
Field], ErrorDiag>;
18861900
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18871901
let Documentation = [IntelFPGASinglePumpAttrDocs];
18881902
}
18891903

18901904
def IntelFPGAMemory : Attr {
1891-
let Spellings = [CXX11<"intelfpga", "memory">];
1905+
let Spellings = [CXX11<"intelfpga", "memory">,
1906+
CXX11<"intel", "fpga_memory">];
18921907
let Args = [EnumArgument<"Kind", "MemoryKind",
18931908
["MLAB", "BLOCK_RAM", ""],
18941909
["MLAB", "BlockRAM", "Default"], 1>];
@@ -1908,7 +1923,8 @@ def IntelFPGAMemory : Attr {
19081923
}
19091924

19101925
def IntelFPGARegister : Attr {
1911-
let Spellings = [CXX11<"intelfpga", "register">];
1926+
let Spellings = [CXX11<"intelfpga", "register">,
1927+
CXX11<"intel", "fpga_register">];
19121928
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19131929
Field], ErrorDiag>;
19141930
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -1917,7 +1933,8 @@ def IntelFPGARegister : Attr {
19171933

19181934
// One integral argument.
19191935
def IntelFPGABankWidth : Attr {
1920-
let Spellings = [CXX11<"intelfpga","bankwidth">];
1936+
let Spellings = [CXX11<"intelfpga","bankwidth">,
1937+
CXX11<"intel","bankwidth">];
19211938
let Args = [ExprArgument<"Value">];
19221939
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19231940
Field], ErrorDiag>;
@@ -1934,7 +1951,8 @@ def IntelFPGABankWidth : Attr {
19341951
}
19351952

19361953
def IntelFPGANumBanks : Attr {
1937-
let Spellings = [CXX11<"intelfpga","numbanks">];
1954+
let Spellings = [CXX11<"intelfpga","numbanks">,
1955+
CXX11<"intel","numbanks">];
19381956
let Args = [ExprArgument<"Value">];
19391957
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19401958
Field], ErrorDiag>;
@@ -1951,7 +1969,8 @@ def IntelFPGANumBanks : Attr {
19511969
}
19521970

19531971
def IntelFPGAPrivateCopies : InheritableAttr {
1954-
let Spellings = [CXX11<"intelfpga","private_copies">];
1972+
let Spellings = [CXX11<"intelfpga","private_copies">,
1973+
CXX11<"intel","private_copies">];
19551974
let Args = [ExprArgument<"Value">];
19561975
let LangOpts = [SYCLIsDevice, SYCLIsHost];
19571976
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
@@ -1968,7 +1987,8 @@ def IntelFPGAPrivateCopies : InheritableAttr {
19681987

19691988
// Two string arguments.
19701989
def IntelFPGAMerge : Attr {
1971-
let Spellings = [CXX11<"intelfpga","merge">];
1990+
let Spellings = [CXX11<"intelfpga","merge">,
1991+
CXX11<"intel","merge">];
19721992
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
19731993
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19741994
Field], ErrorDiag>;
@@ -1977,7 +1997,8 @@ def IntelFPGAMerge : Attr {
19771997
}
19781998

19791999
def IntelFPGAMaxReplicates : Attr {
1980-
let Spellings = [CXX11<"intelfpga","max_replicates">];
2000+
let Spellings = [CXX11<"intelfpga","max_replicates">,
2001+
CXX11<"intel","max_replicates">];
19812002
let Args = [ExprArgument<"Value">];
19822003
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19832004
Field], ErrorDiag>;
@@ -1994,7 +2015,8 @@ def IntelFPGAMaxReplicates : Attr {
19942015
}
19952016

19962017
def IntelFPGASimpleDualPort : Attr {
1997-
let Spellings = [CXX11<"intelfpga","simple_dual_port">];
2018+
let Spellings = [CXX11<"intelfpga","simple_dual_port">,
2019+
CXX11<"intel","simple_dual_port">];
19982020
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19992021
Field], ErrorDiag>;
20002022
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -2019,7 +2041,8 @@ def SYCLIntelPipeIO : Attr {
20192041

20202042
// Variadic integral arguments.
20212043
def IntelFPGABankBits : Attr {
2022-
let Spellings = [CXX11<"intelfpga", "bank_bits">];
2044+
let Spellings = [CXX11<"intelfpga", "bank_bits">,
2045+
CXX11<"intel", "bank_bits">];
20232046
let Args = [VariadicExprArgument<"Args">];
20242047
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20252048
Field], ErrorDiag>;
@@ -2036,7 +2059,8 @@ def IntelFPGABankBits : Attr {
20362059
}
20372060

20382061
def IntelFPGAForcePow2Depth : Attr {
2039-
let Spellings = [CXX11<"intelfpga","force_pow2_depth">];
2062+
let Spellings = [CXX11<"intelfpga","force_pow2_depth">,
2063+
CXX11<"intel","force_pow2_depth">];
20402064
let Args = [ExprArgument<"Value">];
20412065
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20422066
Field], ErrorDiag>;

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