Skip to content

Commit 6212987

Browse files
arsenmarsenm
committed
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
Fixes selection for scalar G_SMULH/G_UMULH. Also switches to using tablegen selected add/sub, which switch to the signed version of the opcode. This matches the current DAG behavior. We can't drop the manual selection for add/sub yet, because it's still both for VALU add/sub and for G_PTR_ADD.
1 parent b136238 commit 6212987

13 files changed

+206
-154
lines changed

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -412,8 +412,14 @@ class UniformUnaryFrag<SDPatternOperator Op> : PatFrag <
412412
class UniformBinFrag<SDPatternOperator Op> : PatFrag <
413413
(ops node:$src0, node:$src1),
414414
(Op $src0, $src1),
415-
[{ return !N->isDivergent(); }]
416-
>;
415+
[{ return !N->isDivergent(); }]> {
416+
// This check is unnecessary as it's captured by the result register
417+
// bank constraint.
418+
//
419+
// FIXME: Should add a way for the emitter to recognize this is a
420+
// trivially true predicate to eliminate the check.
421+
let GISelPredicateCode = [{return true;}];
422+
}
417423

418424
let Defs = [SCC] in { // Carry out goes to SCC
419425
let isCommutable = 1 in {

‎llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -979,7 +979,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec,
979979
; GPRIDX: ; %bb.0: ; %entry
980980
; GPRIDX-NEXT: s_mov_b32 s0, s2
981981
; GPRIDX-NEXT: s_mov_b32 s1, s3
982-
; GPRIDX-NEXT: s_add_u32 m0, s18, -1
982+
; GPRIDX-NEXT: s_add_i32 m0, s18, -1
983983
; GPRIDX-NEXT: s_mov_b32 s2, s4
984984
; GPRIDX-NEXT: s_mov_b32 s3, s5
985985
; GPRIDX-NEXT: s_mov_b32 s4, s6
@@ -1001,7 +1001,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec,
10011001
; MOVREL: ; %bb.0: ; %entry
10021002
; MOVREL-NEXT: s_mov_b32 s0, s2
10031003
; MOVREL-NEXT: s_mov_b32 s1, s3
1004-
; MOVREL-NEXT: s_add_u32 m0, s18, -1
1004+
; MOVREL-NEXT: s_add_i32 m0, s18, -1
10051005
; MOVREL-NEXT: s_mov_b32 s2, s4
10061006
; MOVREL-NEXT: s_mov_b32 s3, s5
10071007
; MOVREL-NEXT: s_mov_b32 s4, s6
@@ -1031,7 +1031,7 @@ define double @dyn_extract_v8f64_v_v_offset3(<8 x double> %vec, i32 %sel) {
10311031
; GPRIDX-NEXT: s_mov_b64 s[4:5], exec
10321032
; GPRIDX-NEXT: BB22_1: ; =>This Inner Loop Header: Depth=1
10331033
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v16
1034-
; GPRIDX-NEXT: s_add_u32 s7, s6, 3
1034+
; GPRIDX-NEXT: s_add_i32 s7, s6, 3
10351035
; GPRIDX-NEXT: s_lshl_b32 s7, s7, 1
10361036
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s6, v16
10371037
; GPRIDX-NEXT: s_set_gpr_idx_on s7, gpr_idx(SRC0)
@@ -1056,7 +1056,7 @@ define double @dyn_extract_v8f64_v_v_offset3(<8 x double> %vec, i32 %sel) {
10561056
; MOVREL-NEXT: BB22_1: ; =>This Inner Loop Header: Depth=1
10571057
; MOVREL-NEXT: v_readfirstlane_b32 s6, v16
10581058
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, s6, v16
1059-
; MOVREL-NEXT: s_add_u32 s6, s6, 3
1059+
; MOVREL-NEXT: s_add_i32 s6, s6, 3
10601060
; MOVREL-NEXT: s_lshl_b32 m0, s6, 1
10611061
; MOVREL-NEXT: v_movrels_b32_e32 v17, v0
10621062
; MOVREL-NEXT: v_movrels_b32_e32 v18, v1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2093,7 +2093,7 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
20932093
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec
20942094
; GPRIDX-NEXT: BB32_1: ; =>This Inner Loop Header: Depth=1
20952095
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v18
2096-
; GPRIDX-NEXT: s_add_u32 s3, s2, 1
2096+
; GPRIDX-NEXT: s_add_i32 s3, s2, 1
20972097
; GPRIDX-NEXT: s_lshl_b32 s3, s3, 1
20982098
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v18
20992099
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
@@ -2139,7 +2139,7 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
21392139
; MOVREL-NEXT: v_mov_b32_e32 v19, v0
21402140
; MOVREL-NEXT: v_mov_b32_e32 v33, v14
21412141
; MOVREL-NEXT: v_mov_b32_e32 v32, v13
2142-
; MOVREL-NEXT: s_add_u32 s2, s1, 1
2142+
; MOVREL-NEXT: s_add_i32 s2, s1, 1
21432143
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18
21442144
; MOVREL-NEXT: v_mov_b32_e32 v31, v12
21452145
; MOVREL-NEXT: v_mov_b32_e32 v30, v11

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -17,20 +17,20 @@ body: |
1717
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
1818
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
1919
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20-
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
21-
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
22-
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_U32_]], %7, 0, implicit $exec
20+
; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
21+
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
22+
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_I32_]], %7, 0, implicit $exec
2323
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec
24-
; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit %7, implicit %8, implicit %9
24+
; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit %7, implicit %8, implicit %9
2525
; GFX9-LABEL: name: add_s32
2626
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
2727
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
2828
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
29-
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
30-
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
31-
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_U32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
29+
; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
30+
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
31+
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
3232
; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
33-
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]
33+
; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]
3434
%0:sgpr(s32) = COPY $sgpr0
3535
%1:sgpr(s32) = COPY $sgpr1
3636
%2:vgpr(s32) = COPY $vgpr0
@@ -123,14 +123,14 @@ body: |
123123
; GFX6: liveins: $sgpr0
124124
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
125125
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
126-
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
127-
; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]]
126+
; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
127+
; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]]
128128
; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
129129
; GFX9: liveins: $sgpr0
130130
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
131131
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
132-
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
133-
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]]
132+
; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
133+
; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]]
134134
%0:sgpr(s32) = COPY $sgpr0
135135
%1:sgpr(s32) = G_CONSTANT i32 16
136136
%2:sgpr(s32) = G_ADD %0, %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -123,8 +123,8 @@ body: |
123123
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
124124
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
125125
; CHECK: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def $scc
126-
; CHECK: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[S_BCNT1_I32_B32_]], [[COPY1]], implicit-def $scc
127-
; CHECK: S_ENDPGM 0, implicit [[S_ADD_U32_]]
126+
; CHECK: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BCNT1_I32_B32_]], [[COPY1]], implicit-def $scc
127+
; CHECK: S_ENDPGM 0, implicit [[S_ADD_I32_]]
128128
%0:sgpr(s32) = COPY $sgpr0
129129
%1:sgpr(s32) = COPY $sgpr1
130130
%2:sgpr(s32) = G_CTPOP %0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -316,16 +316,16 @@ body: |
316316
; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
317317
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
318318
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
319-
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
320-
; MOVREL: $m0 = COPY [[S_ADD_U32_]]
319+
; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
320+
; MOVREL: $m0 = COPY [[S_ADD_I32_]]
321321
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
322322
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
323323
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_m1
324324
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
325325
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
326326
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
327-
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
328-
; GPRIDX: $m0 = COPY [[S_ADD_U32_]]
327+
; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
328+
; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
329329
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
330330
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
331331
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
@@ -378,16 +378,16 @@ body: |
378378
; MOVREL: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
379379
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
380380
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
381-
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
382-
; MOVREL: $m0 = COPY [[S_ADD_U32_]]
381+
; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
382+
; MOVREL: $m0 = COPY [[S_ADD_I32_]]
383383
; MOVREL: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
384384
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
385385
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v8s32_idx_offset_8
386386
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
387387
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
388388
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
389-
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
390-
; GPRIDX: $m0 = COPY [[S_ADD_U32_]]
389+
; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
390+
; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
391391
; GPRIDX: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
392392
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
393393
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
@@ -469,16 +469,16 @@ body: |
469469
; MOVREL: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
470470
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
471471
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
472-
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
473-
; MOVREL: $m0 = COPY [[S_ADD_U32_]]
472+
; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
473+
; MOVREL: $m0 = COPY [[S_ADD_I32_]]
474474
; MOVREL: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
475475
; MOVREL: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
476476
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v8s64_idx_offset_m1
477477
; GPRIDX: [[COPY:%[0-9]+]]:sreg_512 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
478478
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
479479
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
480-
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
481-
; GPRIDX: $m0 = COPY [[S_ADD_U32_]]
480+
; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
481+
; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
482482
; GPRIDX: [[S_MOVRELS_B64_:%[0-9]+]]:sreg_64 = S_MOVRELS_B64 [[COPY]].sub0_sub1, implicit $m0, implicit [[COPY]]
483483
; GPRIDX: S_ENDPGM 0, implicit [[S_MOVRELS_B64_]]
484484
%0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -700,16 +700,16 @@ body: |
700700
; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
701701
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
702702
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
703-
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
704-
; MOVREL: $m0 = COPY [[S_ADD_U32_]]
703+
; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
704+
; MOVREL: $m0 = COPY [[S_ADD_I32_]]
705705
; MOVREL: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
706706
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
707707
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_m1
708708
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
709709
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
710710
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967295
711-
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
712-
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 1, implicit-def $m0, implicit $m0
711+
; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
712+
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 1, implicit-def $m0, implicit $m0
713713
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
714714
; GPRIDX: S_SET_GPR_IDX_OFF
715715
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
@@ -764,16 +764,16 @@ body: |
764764
; MOVREL: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
765765
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
766766
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
767-
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
768-
; MOVREL: $m0 = COPY [[S_ADD_U32_]]
767+
; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
768+
; MOVREL: $m0 = COPY [[S_ADD_I32_]]
769769
; MOVREL: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 undef [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
770770
; MOVREL: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
771771
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v8s32_idx_offset_8
772772
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
773773
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
774774
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
775-
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
776-
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 1, implicit-def $m0, implicit $m0
775+
; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
776+
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 1, implicit-def $m0, implicit $m0
777777
; GPRIDX: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 undef [[COPY]].sub0, implicit $exec, implicit [[COPY]], implicit $m0
778778
; GPRIDX: S_SET_GPR_IDX_OFF
779779
; GPRIDX: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -534,17 +534,17 @@ body: |
534534
; MOVREL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
535535
; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
536536
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
537-
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
538-
; MOVREL: $m0 = COPY [[S_ADD_U32_]]
537+
; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
538+
; MOVREL: $m0 = COPY [[S_ADD_I32_]]
539539
; MOVREL: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
540540
; MOVREL: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
541541
; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_8
542542
; GPRIDX: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
543543
; GPRIDX: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
544544
; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
545545
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
546-
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
547-
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_U32_]], 8, implicit-def $m0, implicit $m0
546+
; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
547+
; GPRIDX: S_SET_GPR_IDX_ON [[S_ADD_I32_]], 8, implicit-def $m0, implicit $m0
548548
; GPRIDX: [[V_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0, implicit $exec
549549
; GPRIDX: S_SET_GPR_IDX_OFF
550550
; GPRIDX: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_B32_V8_]]
@@ -603,17 +603,17 @@ body: |
603603
; MOVREL: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
604604
; MOVREL: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
605605
; MOVREL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
606-
; MOVREL: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
607-
; MOVREL: $m0 = COPY [[S_ADD_U32_]]
606+
; MOVREL: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
607+
; MOVREL: $m0 = COPY [[S_ADD_I32_]]
608608
; MOVREL: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
609609
; MOVREL: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
610610
; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_8
611611
; GPRIDX: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
612612
; GPRIDX: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
613613
; GPRIDX: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
614614
; GPRIDX: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 8
615-
; GPRIDX: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
616-
; GPRIDX: $m0 = COPY [[S_ADD_U32_]]
615+
; GPRIDX: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
616+
; GPRIDX: $m0 = COPY [[S_ADD_I32_]]
617617
; GPRIDX: [[S_INDIRECT_REG_WRITE_B32_V8_:%[0-9]+]]:sreg_256 = S_INDIRECT_REG_WRITE_B32_V8 [[COPY]], [[COPY1]], 1, implicit $m0
618618
; GPRIDX: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_B32_V8_]]
619619
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7

0 commit comments

Comments
 (0)