Merge from 'sycl' to 'sycl-web'

Author: iclsrc

.github/workflows/clang-format.yml

@@ -11,17 +11,14 @@ jobs:
     steps:
     - uses: actions/checkout@v2
       with:
-        # checkout PR head
-        ref: '${{github.event.pull_request.head.sha}}'
-    - name: Fetch target branch
-      run: git fetch --no-tags --prune --depth=1 origin +refs/heads/${{github.base_ref}}:refs/remotes/origin/${{github.base_ref}}
+        fetch-depth: 2
 
     - name: Get clang-format first
       run: sudo apt-get install -yqq clang-format-9
 
     - name: Run clang-format for the patch
       run: |
-        git diff -U0 --no-color origin/${{github.base_ref}}...HEAD | ./clang/tools/clang-format/clang-format-diff.py -p1 -binary clang-format-9 > ./clang-format.patch
+        git diff -U0 --no-color ${GITHUB_SHA}^1 ${GITHUB_SHA} -- | ./clang/tools/clang-format/clang-format-diff.py -p1 -binary clang-format-9 > ./clang-format.patch
 
     # Add patch with formatting fixes to CI job artifacts
     - uses: actions/upload-artifact@v1

clang/test/CodeGenSYCL/hier_par.cpp

@@ -16,7 +16,7 @@
 //
 // This is compile-only test for now.
 //
-
+// XFAIL:* 
 #include "sycl.hpp"
 
 using namespace cl::sycl;

llvm-spirv/lib/SPIRV/LLVMToSPIRVDbgTran.cpp

@@ -201,10 +201,12 @@ void LLVMToSPIRVDbgTran::transLocationInfo() {
         SPIRVString *DirAndFile = BM->getString(getFullPath(DL.get()));
         if (File != DirAndFile || LineNo != DL.getLine() ||
             Col != DL.getCol()) {
+          V = SPIRVWriter->getTranslatedValue(&I);
+          if (!V)
+            continue;
           File = DirAndFile;
           LineNo = DL.getLine();
           Col = DL.getCol();
-          V = SPIRVWriter->getTranslatedValue(&I);
           // According to the spec, OpLine for an OpBranch/OpBranchConditional
           // must precede the merge instruction and not the branch instruction
           auto *VPrev = static_cast<SPIRVInstruction *>(V)->getPrevious();

llvm-spirv/lib/SPIRV/OCLUtil.h

@@ -42,6 +42,7 @@
 #include "SPIRVInternal.h"
 #include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Instructions.h"
 #include "llvm/Support/Path.h"
 
 #include <functional>
@@ -984,6 +985,20 @@ template <> inline void SPIRVMap<std::string, Op, OCLOpaqueType>::init() {
   add("opencl.sampler_t", OpTypeSampler);
 }
 
+typedef SPIRVMap<AtomicRMWInst::BinOp, Op> LLVMSPIRVAtomicRmwOpCodeMap;
+template <> inline void LLVMSPIRVAtomicRmwOpCodeMap::init() {
+  add(llvm::AtomicRMWInst::Xchg, OpAtomicExchange);
+  add(llvm::AtomicRMWInst::Add, OpAtomicIAdd);
+  add(llvm::AtomicRMWInst::Sub, OpAtomicISub);
+  add(llvm::AtomicRMWInst::And, OpAtomicAnd);
+  add(llvm::AtomicRMWInst::Or, OpAtomicOr);
+  add(llvm::AtomicRMWInst::Xor, OpAtomicXor);
+  add(llvm::AtomicRMWInst::Max, OpAtomicSMax);
+  add(llvm::AtomicRMWInst::Min, OpAtomicSMin);
+  add(llvm::AtomicRMWInst::UMax, OpAtomicUMax);
+  add(llvm::AtomicRMWInst::UMin, OpAtomicUMin);
+}
+
 } // namespace SPIRV
 
 #endif // SPIRV_OCLUTIL_H

llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

@@ -1223,6 +1223,36 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V,
                            transValue(SF->getOperand(1), BB), Comp, BB));
   }
 
+  if (AtomicRMWInst *ARMW = dyn_cast<AtomicRMWInst>(V)) {
+    AtomicRMWInst::BinOp Op = ARMW->getOperation();
+    if (!BM->getErrorLog().checkError(
+            !AtomicRMWInst::isFPOperation(Op) && Op != AtomicRMWInst::Nand,
+            SPIRVEC_InvalidInstruction,
+            OCLUtil::toString(V) + "\nAtomic " +
+                AtomicRMWInst::getOperationName(Op).str() +
+                " is not supported in SPIR-V!\n"))
+      return nullptr;
+
+    spv::Op OC = LLVMSPIRVAtomicRmwOpCodeMap::map(Op);
+    AtomicOrderingCABI Ordering = llvm::toCABI(ARMW->getOrdering());
+    auto MemSem = OCLMemOrderMap::map(static_cast<OCLMemOrderKind>(Ordering));
+    std::vector<Value *> Operands(4);
+    Operands[0] = ARMW->getPointerOperand();
+    // To get the memory scope argument we might use ARMW->getSyncScopeID(), but
+    // atomicrmw LLVM instruction is not aware of OpenCL(or SPIR-V) memory scope
+    // enumeration. And assuming the produced SPIR-V module will be consumed in
+    // an OpenCL environment, we can use the same memory scope as OpenCL atomic
+    // functions that don't have memory_scope argument i.e. memory_scope_device.
+    // See the OpenCL C specification p6.13.11. "Atomic Functions"
+    Operands[1] = getUInt32(M, spv::ScopeDevice);
+    Operands[2] = getUInt32(M, MemSem);
+    Operands[3] = ARMW->getValOperand();
+    std::vector<SPIRVId> Ops = BM->getIds(transValue(Operands, BB));
+    SPIRVType *Ty = transType(ARMW->getType());
+
+    return mapValue(V, BM->addInstTemplate(OC, Ops, BB, Ty));
+  }
+
   if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(V)) {
     SPIRVValue *BV = transIntrinsicInst(II, BB);
     return BV ? mapValue(V, BV) : nullptr;
@@ -1539,6 +1569,11 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
     SPIRVValue *Op = transValue(II->getArgOperand(0), BB);
     return BM->addUnaryInst(OpBitReverse, Ty, Op, BB);
   }
+  case Intrinsic::sqrt: {
+    return BM->addExtInst(transType(II->getType()),
+                          BM->getExtInstSetId(SPIRVEIS_OpenCL), OpenCLLIB::Sqrt,
+                          {transValue(II->getOperand(0), BB)}, BB);
+  }
   case Intrinsic::ctlz:
   case Intrinsic::cttz: {
     SPIRVWord ExtOp = II->getIntrinsicID() == Intrinsic::ctlz ? OpenCLLIB::Clz
@@ -1561,20 +1596,16 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
                              transValue(II->getArgOperand(2), BB), BB);
   }
   case Intrinsic::memset: {
-    // Generally memset can't be translated with current version of SPIRV spec.
-    // But in most cases it turns out that memset is emited by Clang to do
-    // zero-initializtion in default constructors.
-    // The code below handles only cases with val = 0 and constant len.
+    // Generally there is no direct mapping of memset to SPIR-V.  But it turns
+    // out that memset is emitted by Clang for initialization in default
+    // constructors so we need some basic support.  The code below only handles
+    // cases with constant value and constant length.
     MemSetInst *MSI = cast<MemSetInst>(II);
     Value *Val = MSI->getValue();
     if (!isa<Constant>(Val)) {
       assert(!"Can't translate llvm.memset with non-const `value` argument");
       return nullptr;
     }
-    if (!cast<Constant>(Val)->isZeroValue()) {
-      assert(!"Can't translate llvm.memset with non-zero `value` argument");
-      return nullptr;
-    }
     Value *Len = MSI->getLength();
     if (!isa<ConstantInt>(Len)) {
       assert(!"Can't translate llvm.memset with non-const `length` argument");
@@ -1583,7 +1614,13 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
     uint64_t NumElements = static_cast<ConstantInt *>(Len)->getZExtValue();
     auto *AT = ArrayType::get(Val->getType(), NumElements);
     SPIRVTypeArray *CompositeTy = static_cast<SPIRVTypeArray *>(transType(AT));
-    SPIRVValue *Init = BM->addNullConstant(CompositeTy);
+    SPIRVValue *Init;
+    if (cast<Constant>(Val)->isZeroValue()) {
+      Init = BM->addNullConstant(CompositeTy);
+    } else {
+      std::vector<SPIRVValue *> Elts{NumElements, transValue(Val, BB)};
+      Init = BM->addCompositeConstant(CompositeTy, Elts);
+    }
     SPIRVType *VarTy = transType(PointerType::get(AT, SPIRV::SPIRAS_Constant));
     SPIRVValue *Var =
         BM->addVariable(VarTy, /*isConstant*/ true, spv::LinkageTypeInternal,

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVErrorEnum.h

@@ -12,3 +12,4 @@ _SPIRV_OP(InvalidBitWidth, "Invalid bit width in input:")
 _SPIRV_OP(InvalidModule, "Invalid SPIR-V module:")
 _SPIRV_OP(UnimplementedOpCode, "Unimplemented opcode")
 _SPIRV_OP(FunctionPointers, "Can't translate function pointer:\n")
+_SPIRV_OP(InvalidInstruction, "Can't translate llvm instruction:\n")

llvm-spirv/test/atomicrmw.ll

@@ -0,0 +1,70 @@
+; RUN: llvm-as < %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -to-text %t.spv -o - | FileCheck %s
+
+; CHECK: TypeInt [[Int:[0-9]+]] 32 0
+; CHECK-DAG: Constant [[Int]] [[Scope_Device:[0-9]+]] 1 {{$}}
+; CHECK-DAG: Constant [[Int]] [[MemSem_Relaxed:[0-9]+]] 0
+; CHECK-DAG: Constant [[Int]] [[MemSem_Acquire:[0-9]+]] 2
+; CHECK-DAG: Constant [[Int]] [[MemSem_Release:[0-9]+]] 4 {{$}}
+; CHECK-DAG: Constant [[Int]] [[MemSem_AcquireRelease:[0-9]+]] 8
+; CHECK-DAG: Constant [[Int]] [[MemSem_SequentiallyConsistent:[0-9]+]] 16
+; CHECK-DAG: Constant [[Int]] [[Value:[0-9]+]] 42
+; CHECK: TypeFloat [[Float:[0-9]+]] 32
+; CHECK: Variable {{[0-9]+}} [[Pointer:[0-9]+]]
+; CHECK: Variable {{[0-9]+}} [[FPPointer:[0-9]+]]
+; CHECK: Constant [[Float]] [[FPValue:[0-9]+]] 1109917696
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+@ui = common dso_local addrspace(1) global i32 0, align 4
+@f = common dso_local local_unnamed_addr addrspace(1) global float 0.000000e+00, align 4
+
+; Function Attrs: nounwind
+define dso_local spir_func void @test_atomicrmw() local_unnamed_addr #0 {
+entry:
+  %0 = atomicrmw xchg i32 addrspace(1)* @ui, i32 42 acq_rel
+; CHECK: AtomicExchange [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_AcquireRelease]] [[Value]]
+
+  %1 = atomicrmw xchg float addrspace(1)* @f, float 42.000000e+00 seq_cst
+; CHECK: AtomicExchange [[Float]] {{[0-9]+}} [[FPPointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[FPValue]]
+
+  %2 = atomicrmw add i32 addrspace(1)* @ui, i32 42 monotonic
+; CHECK: AtomicIAdd [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Relaxed]] [[Value]]
+
+  %3 = atomicrmw sub i32 addrspace(1)* @ui, i32 42 acquire
+; CHECK: AtomicISub [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Acquire]] [[Value]]
+
+  %4 = atomicrmw or i32 addrspace(1)* @ui, i32 42 release
+; CHECK: AtomicOr [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Release]] [[Value]]
+
+  %5 = atomicrmw xor i32 addrspace(1)* @ui, i32 42 acq_rel
+; CHECK: AtomicXor [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_AcquireRelease]] [[Value]]
+
+  %6 = atomicrmw and i32 addrspace(1)* @ui, i32 42 seq_cst
+; CHECK: AtomicAnd [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_SequentiallyConsistent]] [[Value]]
+
+  %7 = atomicrmw max i32 addrspace(1)* @ui, i32 42 monotonic
+; CHECK: AtomicSMax [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Relaxed]] [[Value]]
+
+  %8 = atomicrmw min i32 addrspace(1)* @ui, i32 42 acquire
+; CHECK: AtomicSMin [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Acquire]] [[Value]]
+
+  %9 = atomicrmw umax i32 addrspace(1)* @ui, i32 42 release
+; CHECK: AtomicUMax [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_Release]] [[Value]]
+
+  %10 = atomicrmw umin i32 addrspace(1)* @ui, i32 42 acq_rel
+; CHECK: AtomicUMin [[Int]] {{[0-9]+}} [[Pointer]] [[Scope_Device]] [[MemSem_AcquireRelease]] [[Value]]
+
+  ret void
+}
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20c5968e0953d978be4d9d1062801e8758c393b5)"}

llvm-spirv/test/llvm.sqrt.ll

@@ -0,0 +1,46 @@
+; RUN: llvm-as < %s -o %t.bc
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o - | FileCheck %s
+; RUN: spirv-val %t.spv
+
+; CHECK: ExtInstImport [[ExtInstSetId:[0-9]+]] "OpenCL.std"
+; CHECK: TypeFloat [[Float:[0-9]+]] 32
+; CHECK: TypeFloat [[Double:[0-9]+]] 64
+; CHECK: TypeVector [[Double4:[0-9]+]] [[Double]] 4
+; CHECK: Constant [[Float]] [[FloatArg:[0-9]+]]
+; CHECK: Constant [[Double]] [[DoubleArg:[0-9]+]]
+; CHECK: ConstantComposite [[Double4]] [[Double4Arg:[0-9]+]]
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir"
+
+; Function Attrs: noinline nounwind optnone
+define spir_func void @test_sqrt() #0 {
+entry:
+  %0 = call float @llvm.sqrt.f32(float 0x40091EB860000000)
+  %1 = call double @llvm.sqrt.f64(double 2.710000e+00)
+  %2 = call <4 x double> @llvm.sqrt.v4f64(<4 x double> <double 5.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01>)
+; CHECK: ExtInst [[Float]] {{[0-9]+}} [[ExtInstSetId]] sqrt [[FloatArg]]
+; CHECK: ExtInst [[Double]] {{[0-9]+}} [[ExtInstSetId]] sqrt [[DoubleArg]]
+; CHECK: ExtInst [[Double4]] {{[0-9]+}} [[ExtInstSetId]] sqrt [[Double4Arg]]
+  ret void
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare float @llvm.sqrt.f32(float) #1
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare double @llvm.sqrt.f64(double) #1
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare <4 x double> @llvm.sqrt.v4f64(<4 x double>) #1
+
+attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone speculatable willreturn }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git b89131cdda5871731a9139664aef2b70c6d72bbd)"}
+

llvm-spirv/test/negative/atomicrmw-unsupported-operation.ll

@@ -0,0 +1,29 @@
+; RUN: llvm-as < %s -o %t.bc
+; RUN: not --crash llvm-spirv %t.bc -o %t.spv 2>&1 | FileCheck %s
+
+; CHECK: InvalidInstruction: Can't translate llvm instruction:
+; CHECK: atomicrmw nand i32 addrspace(1)* @ui, i32 42 acq_rel
+; CHECK: Atomic nand is not supported in SPIR-V!
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+@ui = common dso_local addrspace(1) global i32 0, align 4
+@f = common dso_local local_unnamed_addr addrspace(1) global float 0.000000e+00, align 4
+
+; Function Attrs: nounwind
+define dso_local spir_func void @test_atomicrmw() local_unnamed_addr #0 {
+entry:
+  %0 = atomicrmw nand i32 addrspace(1)* @ui, i32 42 acq_rel
+  %1 = atomicrmw fadd float addrspace(1)* @f, float 42.000000e+00 seq_cst
+  %2 = atomicrmw fsub float addrspace(1)* @f, float 42.000000e+00 seq_cst
+  ret void
+}
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20c5968e0953d978be4d9d1062801e8758c393b5)"}

llvm-spirv/test/transcoding/llvm.memset.ll

@@ -1,50 +1,58 @@
-;; struct S1
-;; {
-;;   int x;
-;;   int y;
-;;   int z;
-;; };
-;; S1 foo11()
-;; {
-;;   return S1();
-;; }
-
 ; RUN: llvm-as %s -o %t.bc
 ; RUN: llvm-spirv %t.bc -spirv-text -o %t.spt
 ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.bc -o %t.spv
 ; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: spirv-val %t.spv
 ; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
 
 ; CHECK-SPIRV: TypeInt [[Int8:[0-9]+]] 8 0
-; CHECK-SPIRV: Constant {{[0-9]+}} [[Len:[0-9]+]] 12
+; CHECK-SPIRV: Constant {{[0-9]+}} [[Lenmemset21:[0-9]+]] 4
+; CHECK-SPIRV: Constant {{[0-9]+}} [[Lenmemset0:[0-9]+]] 12
+; CHECK-SPIRV: Constant {{[0-9]+}} [[Const21:[0-9]+]] 21
+; CHECK-SPIRV: TypeArray [[Int8x4:[0-9]+]] [[Int8]] [[Lenmemset21]]
 ; CHECK-SPIRV: TypePointer [[Int8Ptr:[0-9]+]] 8 [[Int8]]
-; CHECK-SPIRV: TypeArray [[Int8x12:[0-9]+]] [[Int8]] [[Len]]
+; CHECK-SPIRV: TypeArray [[Int8x12:[0-9]+]] [[Int8]] [[Lenmemset0]]
 ; CHECK-SPIRV: TypePointer [[Int8PtrConst:[0-9]+]] 0 [[Int8]]
+
 ; CHECK-SPIRV: ConstantNull [[Int8x12]] [[Init:[0-9]+]]
 ; CHECK-SPIRV: Variable {{[0-9]+}} [[Val:[0-9]+]] 0 [[Init]]
+; CHECK-SPIRV: 7 ConstantComposite [[Int8x4]] [[InitComp:[0-9]+]] [[Const21]] [[Const21]] [[Const21]] [[Const21]]
+; CHECK-SPIRV: Variable {{[0-9]+}} [[ValComp:[0-9]+]] 0 [[InitComp]]
 
 ; CHECK-SPIRV: Bitcast [[Int8Ptr]] [[Target:[0-9]+]] {{[0-9]+}}
 ; CHECK-SPIRV: Bitcast [[Int8PtrConst]] [[Source:[0-9]+]] [[Val]]
-; CHECK-SPIRV: CopyMemorySized [[Target]] [[Source]] [[Len]] 2 4
+; CHECK-SPIRV: CopyMemorySized [[Target]] [[Source]] [[Lenmemset0]] 2 4
 
+; CHECK-SPIRV: Bitcast [[Int8PtrConst]] [[SourceComp:[0-9]+]] [[ValComp]]
+; CHECK-SPIRV: CopyMemorySized {{[0-9]+}} [[SourceComp]] [[Lenmemset21]] 2 4
 
 target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
 target triple = "spir"
 
 %struct.S1 = type { i32, i32, i32 }
 
+; CHECK-LLVM: internal unnamed_addr addrspace(2) constant [12 x i8] zeroinitializer
+; CHECK-LLVM: internal unnamed_addr addrspace(2) constant [4 x i8] c"\15\15\15\15"
+
 ; Function Attrs: nounwind
 define spir_func void @_Z5foo11v(%struct.S1 addrspace(4)* noalias nocapture sret %agg.result) #0 {
+  %x = alloca [4 x i8]
+  %x.bc = bitcast [4 x i8]* %x to i8*
   %1 = bitcast %struct.S1 addrspace(4)* %agg.result to i8 addrspace(4)*
   tail call void @llvm.memset.p4i8.i32(i8 addrspace(4)* align 4 %1, i8 0, i32 12, i1 false)
 ; CHECK-LLVM: call void @llvm.memset.p4i8.i32(i8 addrspace(4)* align 4 %1, i8 0, i32 12, i1 false)
+  tail call void @llvm.memset.p0i8.i32(i8* align 4 %x.bc, i8 21, i32 4, i1 false)
+; CHECK-LLVM: call void @llvm.memcpy.p0i8.p2i8.i32(i8* align 4 %x.bc, i8 addrspace(2)* align 4 %3, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind
 declare void @llvm.memset.p4i8.i32(i8 addrspace(4)* nocapture, i8, i32, i1) #1
 
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) #1
+
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind }