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Simon Moll
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[VP,Integer,#1] Vector-predicated integer intrinsics
Summary: This patch adds IR intrinsics for vector-predicated integer arithmetic. It is subpatch #1 of the [integer slice](https://reviews.llvm.org/D57504#1732277) of [LLVM-VP](https://reviews.llvm.org/D57504). LLVM-VP is a larger effort to bring native vector predication to LLVM. Reviewed By: andrew.w.kaylor Differential Revision: https://reviews.llvm.org/D69891
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‎llvm/docs/LangRef.rst

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‎llvm/include/llvm/Analysis/TargetTransformInfo.h

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@@ -1167,6 +1167,15 @@ class TargetTransformInfo {
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/// to a stack reload.
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unsigned getGISelRematGlobalCost() const;
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/// \name Vector Predication Information
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/// @{
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/// Whether the target supports the %evl parameter of VP intrinsic efficiently in hardware.
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/// (see LLVM Language Reference - "Vector Predication Intrinsics")
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/// Use of %evl is discouraged when that is not the case.
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bool hasActiveVectorLength() const;
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/// @}
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/// @}
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private:
@@ -1420,6 +1429,7 @@ class TargetTransformInfo::Concept {
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ReductionFlags) const = 0;
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virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0;
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virtual unsigned getGISelRematGlobalCost() const = 0;
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virtual bool hasActiveVectorLength() const = 0;
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virtual int getInstructionLatency(const Instruction *I) = 0;
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};
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@@ -1913,6 +1923,10 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
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return Impl.getGISelRematGlobalCost();
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}
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bool hasActiveVectorLength() const override {
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return Impl.hasActiveVectorLength();
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}
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int getInstructionLatency(const Instruction *I) override {
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return Impl.getInstructionLatency(I);
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}

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

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@@ -628,6 +628,10 @@ class TargetTransformInfoImplBase {
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return 1;
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}
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bool hasActiveVectorLength() const {
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return false;
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}
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protected:
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// Obtain the minimum required size to hold the value (without the sign)
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// In case of a vector it returns the min required size for one element.

‎llvm/include/llvm/IR/IntrinsicInst.h

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@@ -206,6 +206,48 @@ namespace llvm {
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/// @}
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};
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/// This is the common base class for vector predication intrinsics.
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class VPIntrinsic : public IntrinsicInst {
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public:
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static Optional<int> GetMaskParamPos(Intrinsic::ID IntrinsicID);
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static Optional<int> GetVectorLengthParamPos(Intrinsic::ID IntrinsicID);
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/// The llvm.vp.* intrinsics for this instruction Opcode
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static Intrinsic::ID GetForOpcode(unsigned OC);
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// Whether \p ID is a VP intrinsic ID.
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static bool IsVPIntrinsic(Intrinsic::ID);
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/// \return the mask parameter or nullptr.
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Value *getMaskParam() const;
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/// \return the vector length parameter or nullptr.
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Value *getVectorLengthParam() const;
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/// \return whether the vector length param can be ignored.
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bool canIgnoreVectorLengthParam() const;
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/// \return the static element count (vector number of elements) the vector
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/// length parameter applies to.
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ElementCount getStaticVectorLength() const;
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// Methods for support type inquiry through isa, cast, and dyn_cast:
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static bool classof(const IntrinsicInst *I) {
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return IsVPIntrinsic(I->getIntrinsicID());
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}
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static bool classof(const Value *V) {
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return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
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}
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// Equivalent non-predicated opcode
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unsigned getFunctionalOpcode() const {
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return GetFunctionalOpcodeForVP(getIntrinsicID());
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}
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// Equivalent non-predicated opcode
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static unsigned GetFunctionalOpcodeForVP(Intrinsic::ID ID);
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};
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/// This is the common base class for constrained floating point intrinsics.
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class ConstrainedFPIntrinsic : public IntrinsicInst {
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public:

‎llvm/include/llvm/IR/Intrinsics.td

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@@ -27,6 +27,10 @@ class IntrinsicProperty;
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// effects. It may be CSE'd deleted if dead, etc.
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def IntrNoMem : IntrinsicProperty;
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// IntrNoSync - Threads executing the intrinsic will not synchronize using
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// memory or other means.
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def IntrNoSync : IntrinsicProperty;
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// IntrReadMem - This intrinsic only reads from memory. It does not write to
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// memory and has no other side effects. Therefore, it cannot be moved across
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// potentially aliasing stores. However, it can be reordered otherwise and can
@@ -1153,6 +1157,79 @@ def int_is_constant : Intrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem, IntrWil
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def int_ptrmask: Intrinsic<[llvm_anyptr_ty], [llvm_anyptr_ty, llvm_anyint_ty],
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[IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
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//===---------------- Vector Predication Intrinsics --------------===//
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// Binary operators
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let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in {
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def int_vp_add : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_sub : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_mul : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_sdiv : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_udiv : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_srem : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_urem : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_ashr : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_lshr : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_shl : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_or : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_and : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_xor : Intrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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}
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//===-------------------------- Masked Intrinsics -------------------------===//
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//
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def int_masked_store : Intrinsic<[], [llvm_anyvector_ty,

‎llvm/include/llvm/IR/VPIntrinsics.def

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@@ -0,0 +1,84 @@
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//===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains descriptions of the various Vector Predication intrinsics.
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// This is used as a central place for enumerating the different instructions
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// and should eventually be the place to put comments about the instructions.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: NO INCLUDE GUARD DESIRED!
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// Provide definitions of macros so that users of this file do not have to
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// define everything to use it...
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//
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#ifndef REGISTER_VP_INTRINSIC
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#define REGISTER_VP_INTRINSIC(VPID, MASKPOS, VLENPOS)
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#endif
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// Map this VP intrinsic to its functional Opcode
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#ifndef HANDLE_VP_TO_OC
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#define HANDLE_VP_TO_OC(VPID, OC)
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#endif
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///// Integer Arithmetic /////
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// llvm.vp.add(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_add, 2, 3)
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HANDLE_VP_TO_OC(vp_add, Add)
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// llvm.vp.and(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_and, 2, 3)
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HANDLE_VP_TO_OC(vp_and, And)
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// llvm.vp.ashr(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_ashr, 2, 3)
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HANDLE_VP_TO_OC(vp_ashr, AShr)
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// llvm.vp.lshr(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_lshr, 2, 3)
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HANDLE_VP_TO_OC(vp_lshr, LShr)
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// llvm.vp.mul(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_mul, 2, 3)
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HANDLE_VP_TO_OC(vp_mul, Mul)
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// llvm.vp.or(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_or, 2, 3)
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HANDLE_VP_TO_OC(vp_or, Or)
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// llvm.vp.sdiv(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_sdiv, 2, 3)
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HANDLE_VP_TO_OC(vp_sdiv, SDiv)
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// llvm.vp.shl(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_shl, 2, 3)
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HANDLE_VP_TO_OC(vp_shl, Shl)
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// llvm.vp.srem(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_srem, 2, 3)
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HANDLE_VP_TO_OC(vp_srem, SRem)
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// llvm.vp.sub(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_sub, 2, 3)
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HANDLE_VP_TO_OC(vp_sub, Sub)
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// llvm.vp.udiv(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_udiv, 2, 3)
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HANDLE_VP_TO_OC(vp_udiv, UDiv)
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// llvm.vp.urem(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_urem, 2, 3)
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HANDLE_VP_TO_OC(vp_urem, URem)
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// llvm.vp.xor(x,y,mask,vlen)
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REGISTER_VP_INTRINSIC(vp_xor, 2, 3)
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HANDLE_VP_TO_OC(vp_xor, Xor)
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#undef REGISTER_VP_INTRINSIC
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#undef HANDLE_VP_TO_OC

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