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Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"
This reverts commit f5cd7ec. Certain rocPRIM/rocThrust/hipCUB tests were failing because of this change.
1 parent 6199219 commit 8b08fa0

16 files changed

+61
-78
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 14 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
9090
def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
9191
"UnalignedBufferAccess",
9292
"true",
93-
"Hardware supports unaligned global loads and stores"
93+
"Support unaligned global loads and stores"
9494
>;
9595

9696
def FeatureTrapHandler: SubtargetFeature<"trap-handler",
@@ -105,10 +105,18 @@ def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
105105
"Support unaligned scratch loads and stores"
106106
>;
107107

108+
// LDS alignment enforcement is controlled by a configuration register:
109+
// SH_MEM_CONFIG.alignment_mode
110+
def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
111+
"UnalignedAccessMode",
112+
"true",
113+
"Support unaligned local and region loads and stores"
114+
>;
115+
108116
def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
109117
"UnalignedDSAccess",
110118
"true",
111-
"Hardware supports unaligned local and region loads and stores"
119+
"Does not requires 16 byte alignment for certain local and region loads and stores"
112120
>;
113121

114122
def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
@@ -645,15 +653,6 @@ def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
645653
"Requires use of fract on arguments to trig instructions"
646654
>;
647655

648-
// Alignment enforcement is controlled by a configuration register:
649-
// SH_MEM_CONFIG.alignment_mode
650-
def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
651-
"UnalignedAccessMode",
652-
"true",
653-
"Enable unaligned global, local and region loads and stores if the hardware"
654-
" supports it"
655-
>;
656-
657656
// Dummy feature used to disable assembler instructions.
658657
def FeatureDisable : SubtargetFeature<"",
659658
"FeatureDisable","true",
@@ -680,8 +679,7 @@ def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
680679
FeatureWavefrontSize64, FeatureFlatAddressSpace,
681680
FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
682681
FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
683-
FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC,
684-
FeatureUnalignedBufferAccess]
682+
FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC]
685683
>;
686684

687685
def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
@@ -694,8 +692,7 @@ def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
694692
FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
695693
FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
696694
FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
697-
FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32,
698-
FeatureUnalignedBufferAccess
695+
FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32
699696
]
700697
>;
701698

@@ -712,8 +709,7 @@ def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
712709
FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
713710
FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
714711
FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts,
715-
FeatureFastDenormalF32, FeatureUnalignedBufferAccess,
716-
FeatureUnalignedDSAccess
712+
FeatureFastDenormalF32, FeatureUnalignedDSAccess
717713
]
718714
>;
719715

@@ -732,7 +728,7 @@ def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
732728
FeatureVOP3Literal, FeatureDPP8,
733729
FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC,
734730
FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16,
735-
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
731+
FeatureUnalignedDSAccess
736732
]
737733
>;
738734

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1068,9 +1068,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
10681068
return false;
10691069
};
10701070

1071-
unsigned GlobalAlign32 = ST.hasUnalignedBufferAccessEnabled() ? 0 : 32;
1072-
unsigned GlobalAlign16 = ST.hasUnalignedBufferAccessEnabled() ? 0 : 16;
1073-
unsigned GlobalAlign8 = ST.hasUnalignedBufferAccessEnabled() ? 0 : 8;
1071+
unsigned GlobalAlign32 = ST.hasUnalignedBufferAccess() ? 0 : 32;
1072+
unsigned GlobalAlign16 = ST.hasUnalignedBufferAccess() ? 0 : 16;
1073+
unsigned GlobalAlign8 = ST.hasUnalignedBufferAccess() ? 0 : 8;
10741074

10751075
// TODO: Refine based on subtargets which support unaligned access or 128-bit
10761076
// LDS

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
8181
SmallString<256> FullFS("+promote-alloca,+load-store-opt,+enable-ds128,+sram-ecc,+xnack,");
8282

8383
if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
84-
FullFS += "+flat-for-global,+unaligned-access-mode,+trap-handler,";
84+
FullFS += "+flat-for-global,+unaligned-buffer-access,+trap-handler,";
8585

8686
FullFS += "+enable-prt-strict-null,"; // This is overridden by a disable in FS
8787

@@ -186,6 +186,7 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
186186
AutoWaitcntBeforeBarrier(false),
187187
CodeObjectV3(false),
188188
UnalignedScratchAccess(false),
189+
UnalignedBufferAccess(false),
189190
UnalignedAccessMode(false),
190191

191192
HasApertureRegs(false),
@@ -257,7 +258,6 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
257258
HasUnpackedD16VMem(false),
258259
LDSMisalignedBug(false),
259260
HasMFMAInlineLiteralBug(false),
260-
UnalignedBufferAccess(false),
261261
UnalignedDSAccess(false),
262262

263263
ScalarizeGlobal(false),

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,7 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
318318
bool AutoWaitcntBeforeBarrier;
319319
bool CodeObjectV3;
320320
bool UnalignedScratchAccess;
321+
bool UnalignedBufferAccess;
321322
bool UnalignedAccessMode;
322323
bool HasApertureRegs;
323324
bool EnableXNACK;
@@ -398,7 +399,6 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
398399
bool HasMFMAInlineLiteralBug;
399400
bool HasVertexCache;
400401
short TexVTXClauseSize;
401-
bool UnalignedBufferAccess;
402402
bool UnalignedDSAccess;
403403
bool ScalarizeGlobal;
404404

@@ -706,18 +706,6 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
706706
return UnalignedBufferAccess;
707707
}
708708

709-
bool hasUnalignedBufferAccessEnabled() const {
710-
return UnalignedBufferAccess && UnalignedAccessMode;
711-
}
712-
713-
bool hasUnalignedDSAccess() const {
714-
return UnalignedDSAccess;
715-
}
716-
717-
bool hasUnalignedDSAccessEnabled() const {
718-
return UnalignedDSAccess && UnalignedAccessMode;
719-
}
720-
721709
bool hasUnalignedScratchAccess() const {
722710
return UnalignedScratchAccess;
723711
}
@@ -726,6 +714,10 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
726714
return UnalignedAccessMode;
727715
}
728716

717+
bool hasUnalignedDSAccess() const {
718+
return UnalignedDSAccess;
719+
}
720+
729721
bool hasApertureRegs() const {
730722
return HasApertureRegs;
731723
}

‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
8888
AMDGPU::FeatureEnableUnsafeDSOffsetFolding,
8989
AMDGPU::FeatureFlatForGlobal,
9090
AMDGPU::FeaturePromoteAlloca,
91+
AMDGPU::FeatureUnalignedBufferAccess,
9192
AMDGPU::FeatureUnalignedScratchAccess,
9293
AMDGPU::FeatureUnalignedAccessMode,
9394

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1433,7 +1433,8 @@ bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
14331433
AddrSpace == AMDGPUAS::REGION_ADDRESS) {
14341434
// Check if alignment requirements for ds_read/write instructions are
14351435
// disabled.
1436-
if (Subtarget->hasUnalignedDSAccessEnabled() &&
1436+
if (Subtarget->hasUnalignedDSAccess() &&
1437+
Subtarget->hasUnalignedAccessMode() &&
14371438
!Subtarget->hasLDSMisalignedBug()) {
14381439
if (IsFast)
14391440
*IsFast = Alignment != Align(2);
@@ -1483,7 +1484,7 @@ bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
14831484
return AlignedBy4;
14841485
}
14851486

1486-
if (Subtarget->hasUnalignedBufferAccessEnabled() &&
1487+
if (Subtarget->hasUnalignedBufferAccess() &&
14871488
!(AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
14881489
AddrSpace == AMDGPUAS::REGION_ADDRESS)) {
14891490
// If we have an uniform constant load, it still requires using a slow

‎llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-UNALIGNED %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-NOUNALIGNED %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-UNALIGNED %s
5-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=-unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-NOUNALIGNED %s
2+
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-UNALIGNED %s
3+
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-NOUNALIGNED %s
4+
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-UNALIGNED %s
5+
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-NOUNALIGNED %s
66

77
; FIXME:
88
; XUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s

‎llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
2-
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s
2+
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s
33
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC
4-
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s
5-
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
6-
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s
7-
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
4+
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s
5+
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
6+
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s
7+
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
88

99
; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s
1010
; RUN: opt -S -mtriple=amdgcn-unknown-unknown -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s

‎llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -mattr=-unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX900 %s
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900 %s
33

44
define <2 x half> @chain_hi_to_lo_private() {
55
; GCN-LABEL: chain_hi_to_lo_private:

‎llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=-unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX7-ALIGNED %s
3-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX7-UNALIGNED %s
4-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,GFX9 %s
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7-ALIGNED %s
3+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7-UNALIGNED %s
4+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9 %s
55

66
; Should not merge this to a dword load
77
define i32 @global_load_2xi16_align2(i16 addrspace(1)* %p) #0 {

‎llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s
2-
; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=+unaligned-access-mode -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=UNALIGNED %s
2+
; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=+unaligned-buffer-access -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=UNALIGNED %s
33
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s
44

55
; SI-LABEL: {{^}}local_unaligned_load_store_i16:

‎llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=none -o - %s | FileCheck -check-prefix=MCPU %s
2-
# RUN: llc -march=amdgcn -mattr=+unaligned-access-mode -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
2+
# RUN: llc -march=amdgcn -mattr=+unaligned-buffer-access -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
33

44
# FIXME: This overrides attributes that already are present. It should probably
55
# only touch functions without an existing attribute.
@@ -10,8 +10,8 @@
1010
# MCPU: attributes #0 = { "target-cpu"="fiji" }
1111
# MCPU: attributes #1 = { "target-cpu"="hawaii" }
1212

13-
# MATTR: attributes #0 = { "target-cpu"="fiji" "target-features"="+unaligned-access-mode" }
14-
# MATTR: attributes #1 = { "target-features"="+unaligned-access-mode" }
13+
# MATTR: attributes #0 = { "target-cpu"="fiji" "target-features"="+unaligned-buffer-access" }
14+
# MATTR: attributes #1 = { "target-features"="+unaligned-buffer-access" }
1515

1616
--- |
1717
define amdgpu_kernel void @with_cpu_attr() #0 {

‎llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=none -o - %s | FileCheck -check-prefix=MCPU %s
2-
# RUN: llc -march=amdgcn -mattr=+unaligned-access-mode -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
2+
# RUN: llc -march=amdgcn -mattr=+unaligned-buffer-access -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
33

44
# The command line arguments for -mcpu and -mattr should manifest themselves by adding the corresponding attributes to the stub IR function.
55

66
# MCPU: attributes #0 = { "target-cpu"="hawaii" }
7-
# MATTR: attributes #0 = { "target-features"="+unaligned-access-mode" }
7+
# MATTR: attributes #0 = { "target-features"="+unaligned-buffer-access" }
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---
1010
name: no_ir

‎llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
; RUN: opt -S -load-store-vectorizer --mcpu=hawaii -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s
2-
; RUN: opt -S -load-store-vectorizer --mcpu=hawaii -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s
3-
; RUN: opt -S -passes='function(load-store-vectorizer)' --mcpu=hawaii -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s
4-
; RUN: opt -S -passes='function(load-store-vectorizer)' --mcpu=hawaii -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s
1+
; RUN: opt -S -load-store-vectorizer -mattr=-unaligned-buffer-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s
2+
; RUN: opt -S -load-store-vectorizer -mattr=+unaligned-buffer-access,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s
3+
; RUN: opt -S -passes='function(load-store-vectorizer)' -mattr=-unaligned-buffer-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s
4+
; RUN: opt -S -passes='function(load-store-vectorizer)' -mattr=+unaligned-buffer-access,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s
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target triple = "amdgcn--"
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"

‎llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: opt -mtriple=amdgcn-amd-amdhsa --mcpu=hawaii -load-store-vectorizer -S -o - %s | FileCheck %s
1+
; RUN: opt -mtriple=amdgcn-amd-amdhsa -load-store-vectorizer -S -o - %s | FileCheck %s
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; Copy of test/CodeGen/AMDGPU/merge-stores.ll with some additions
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"

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