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[Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns
This should handle the basic integer min/max handling - the HVX ops are still TODO. This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876. Differential Revision: https://reviews.llvm.org/D92112
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3 files changed

+49
-46
lines changed

3 files changed

+49
-46
lines changed

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1517,8 +1517,11 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
15171517
setMinimumJumpTableEntries(std::numeric_limits<unsigned>::max());
15181518
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
15191519

1520-
setOperationAction(ISD::ABS, MVT::i32, Legal);
1521-
setOperationAction(ISD::ABS, MVT::i64, Legal);
1520+
for (unsigned LegalIntOp :
1521+
{ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) {
1522+
setOperationAction(LegalIntOp, MVT::i32, Legal);
1523+
setOperationAction(LegalIntOp, MVT::i64, Legal);
1524+
}
15221525

15231526
// Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
15241527
// but they only operate on i64.
@@ -1683,6 +1686,13 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
16831686
setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal);
16841687
}
16851688

1689+
for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1690+
setOperationAction(ISD::SMIN, VT, Legal);
1691+
setOperationAction(ISD::SMAX, VT, Legal);
1692+
setOperationAction(ISD::UMIN, VT, Legal);
1693+
setOperationAction(ISD::UMAX, VT, Legal);
1694+
}
1695+
16861696
// Custom lower unaligned loads.
16871697
// Also, for both loads and stores, verify the alignment of the address
16881698
// in case it is a compile-time constant. This is a usability feature to

‎llvm/lib/Target/Hexagon/HexagonPatterns.td

Lines changed: 25 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -366,12 +366,14 @@ multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> {
366366
def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>;
367367
}
368368

369-
370369
// Frags for commonly used SDNodes.
371370
def Add: pf2<add>; def And: pf2<and>; def Sra: pf2<sra>;
372371
def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
373372
def Mul: pf2<mul>; def Xor: pf2<xor>; def Shl: pf2<shl>;
374373

374+
def Smin: pf2<smin>; def Smax: pf2<smax>;
375+
def Umin: pf2<umin>; def Umax: pf2<umax>;
376+
375377
def Rol: pf2<rotl>;
376378

377379
// --(1) Immediate -------------------------------------------------------
@@ -924,25 +926,14 @@ let AddedComplexity = 200 in {
924926
defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>;
925927
}
926928

927-
let AddedComplexity = 200 in {
928-
defm: MinMax_pats<A2_min, A2_max, select, setgt, i1, I32>;
929-
defm: MinMax_pats<A2_min, A2_max, select, setge, i1, I32>;
930-
defm: MinMax_pats<A2_max, A2_min, select, setlt, i1, I32>;
931-
defm: MinMax_pats<A2_max, A2_min, select, setle, i1, I32>;
932-
defm: MinMax_pats<A2_minu, A2_maxu, select, setugt, i1, I32>;
933-
defm: MinMax_pats<A2_minu, A2_maxu, select, setuge, i1, I32>;
934-
defm: MinMax_pats<A2_maxu, A2_minu, select, setult, i1, I32>;
935-
defm: MinMax_pats<A2_maxu, A2_minu, select, setule, i1, I32>;
936-
937-
defm: MinMax_pats<A2_minp, A2_maxp, select, setgt, i1, I64>;
938-
defm: MinMax_pats<A2_minp, A2_maxp, select, setge, i1, I64>;
939-
defm: MinMax_pats<A2_maxp, A2_minp, select, setlt, i1, I64>;
940-
defm: MinMax_pats<A2_maxp, A2_minp, select, setle, i1, I64>;
941-
defm: MinMax_pats<A2_minup, A2_maxup, select, setugt, i1, I64>;
942-
defm: MinMax_pats<A2_minup, A2_maxup, select, setuge, i1, I64>;
943-
defm: MinMax_pats<A2_maxup, A2_minup, select, setult, i1, I64>;
944-
defm: MinMax_pats<A2_maxup, A2_minup, select, setule, i1, I64>;
945-
}
929+
def: OpR_RR_pat<A2_min, Smin, i32, I32, I32>;
930+
def: OpR_RR_pat<A2_max, Smax, i32, I32, I32>;
931+
def: OpR_RR_pat<A2_minu, Umin, i32, I32, I32>;
932+
def: OpR_RR_pat<A2_maxu, Umax, i32, I32, I32>;
933+
def: OpR_RR_pat<A2_minp, Smin, i64, I64, I64>;
934+
def: OpR_RR_pat<A2_maxp, Smax, i64, I64, I64>;
935+
def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>;
936+
def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>;
946937

947938
let AddedComplexity = 100 in {
948939
defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>;
@@ -958,18 +949,20 @@ let AddedComplexity = 100, Predicates = [HasV67] in {
958949
defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>;
959950
}
960951

961-
defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setgt, v8i1, V8I8>;
962-
defm: MinMax_pats<A2_vminb, A2_vmaxb, vselect, setge, v8i1, V8I8>;
963-
defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setgt, v4i1, V4I16>;
964-
defm: MinMax_pats<A2_vminh, A2_vmaxh, vselect, setge, v4i1, V4I16>;
965-
defm: MinMax_pats<A2_vminw, A2_vmaxw, vselect, setgt, v2i1, V2I32>;
966-
defm: MinMax_pats<A2_vminw, A2_vmaxw, vselect, setge, v2i1, V2I32>;
967-
defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setugt, v8i1, V8I8>;
968-
defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setuge, v8i1, V8I8>;
969-
defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setugt, v4i1, V4I16>;
970-
defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setuge, v4i1, V4I16>;
971-
defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setugt, v2i1, V2I32>;
972-
defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setuge, v2i1, V2I32>;
952+
def: OpR_RR_pat<A2_vminb, Smin, v8i8, V8I8>;
953+
def: OpR_RR_pat<A2_vmaxb, Smax, v8i8, V8I8>;
954+
def: OpR_RR_pat<A2_vminub, Umin, v8i8, V8I8>;
955+
def: OpR_RR_pat<A2_vmaxub, Umax, v8i8, V8I8>;
956+
957+
def: OpR_RR_pat<A2_vminh, Smin, v4i16, V4I16>;
958+
def: OpR_RR_pat<A2_vmaxh, Smax, v4i16, V4I16>;
959+
def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>;
960+
def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>;
961+
962+
def: OpR_RR_pat<A2_vminw, Smin, v2i32, V2I32>;
963+
def: OpR_RR_pat<A2_vmaxw, Smax, v2i32, V2I32>;
964+
def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>;
965+
def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>;
973966

974967
// --(7) Insert/extract --------------------------------------------------
975968
//

‎llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; min
44

55
; CHECK-LABEL: test_00:
6-
; CHECK: r1:0 = vminb(r3:2,r1:0)
6+
; CHECK: r1:0 = vminb(r1:0,r3:2)
77
define <8 x i8> @test_00(<8 x i8> %a0, <8 x i8> %a1) #0 {
88
%v0 = icmp slt <8 x i8> %a0, %a1
99
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -19,7 +19,7 @@ define <8 x i8> @test_01(<8 x i8> %a0, <8 x i8> %a1) #0 {
1919
}
2020

2121
; CHECK-LABEL: test_02:
22-
; CHECK: r1:0 = vminh(r3:2,r1:0)
22+
; CHECK: r1:0 = vminh(r1:0,r3:2)
2323
define <4 x i16> @test_02(<4 x i16> %a0, <4 x i16> %a1) #0 {
2424
%v0 = icmp slt <4 x i16> %a0, %a1
2525
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -35,7 +35,7 @@ define <4 x i16> @test_03(<4 x i16> %a0, <4 x i16> %a1) #0 {
3535
}
3636

3737
; CHECK-LABEL: test_04:
38-
; CHECK: r1:0 = vminw(r3:2,r1:0)
38+
; CHECK: r1:0 = vminw(r1:0,r3:2)
3939
define <2 x i32> @test_04(<2 x i32> %a0, <2 x i32> %a1) #0 {
4040
%v0 = icmp slt <2 x i32> %a0, %a1
4141
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
@@ -53,7 +53,7 @@ define <2 x i32> @test_05(<2 x i32> %a0, <2 x i32> %a1) #0 {
5353
; minu
5454

5555
; CHECK-LABEL: test_06:
56-
; CHECK: r1:0 = vminub(r3:2,r1:0)
56+
; CHECK: r1:0 = vminub(r1:0,r3:2)
5757
define <8 x i8> @test_06(<8 x i8> %a0, <8 x i8> %a1) #0 {
5858
%v0 = icmp ult <8 x i8> %a0, %a1
5959
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -69,7 +69,7 @@ define <8 x i8> @test_07(<8 x i8> %a0, <8 x i8> %a1) #0 {
6969
}
7070

7171
; CHECK-LABEL: test_08:
72-
; CHECK: r1:0 = vminuh(r3:2,r1:0)
72+
; CHECK: r1:0 = vminuh(r1:0,r3:2)
7373
define <4 x i16> @test_08(<4 x i16> %a0, <4 x i16> %a1) #0 {
7474
%v0 = icmp ult <4 x i16> %a0, %a1
7575
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -85,7 +85,7 @@ define <4 x i16> @test_09(<4 x i16> %a0, <4 x i16> %a1) #0 {
8585
}
8686

8787
; CHECK-LABEL: test_0a:
88-
; CHECK: r1:0 = vminuw(r3:2,r1:0)
88+
; CHECK: r1:0 = vminuw(r1:0,r3:2)
8989
define <2 x i32> @test_0a(<2 x i32> %a0, <2 x i32> %a1) #0 {
9090
%v0 = icmp ult <2 x i32> %a0, %a1
9191
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
@@ -111,7 +111,7 @@ define <8 x i8> @test_0c(<8 x i8> %a0, <8 x i8> %a1) #0 {
111111
}
112112

113113
; CHECK-LABEL: test_0d:
114-
; CHECK: r1:0 = vmaxb(r3:2,r1:0)
114+
; CHECK: r1:0 = vmaxb(r1:0,r3:2)
115115
define <8 x i8> @test_0d(<8 x i8> %a0, <8 x i8> %a1) #0 {
116116
%v0 = icmp sge <8 x i8> %a0, %a1
117117
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -127,7 +127,7 @@ define <4 x i16> @test_0e(<4 x i16> %a0, <4 x i16> %a1) #0 {
127127
}
128128

129129
; CHECK-LABEL: test_0f:
130-
; CHECK: r1:0 = vmaxh(r3:2,r1:0)
130+
; CHECK: r1:0 = vmaxh(r1:0,r3:2)
131131
define <4 x i16> @test_0f(<4 x i16> %a0, <4 x i16> %a1) #0 {
132132
%v0 = icmp sge <4 x i16> %a0, %a1
133133
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -143,7 +143,7 @@ define <2 x i32> @test_10(<2 x i32> %a0, <2 x i32> %a1) #0 {
143143
}
144144

145145
; CHECK-LABEL: test_11:
146-
; CHECK: r1:0 = vmaxw(r3:2,r1:0)
146+
; CHECK: r1:0 = vmaxw(r1:0,r3:2)
147147
define <2 x i32> @test_11(<2 x i32> %a0, <2 x i32> %a1) #0 {
148148
%v0 = icmp sge <2 x i32> %a0, %a1
149149
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
@@ -161,7 +161,7 @@ define <8 x i8> @test_12(<8 x i8> %a0, <8 x i8> %a1) #0 {
161161
}
162162

163163
; CHECK-LABEL: test_13:
164-
; CHECK: r1:0 = vmaxub(r3:2,r1:0)
164+
; CHECK: r1:0 = vmaxub(r1:0,r3:2)
165165
define <8 x i8> @test_13(<8 x i8> %a0, <8 x i8> %a1) #0 {
166166
%v0 = icmp uge <8 x i8> %a0, %a1
167167
%v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
@@ -177,7 +177,7 @@ define <4 x i16> @test_14(<4 x i16> %a0, <4 x i16> %a1) #0 {
177177
}
178178

179179
; CHECK-LABEL: test_15:
180-
; CHECK: r1:0 = vmaxuh(r3:2,r1:0)
180+
; CHECK: r1:0 = vmaxuh(r1:0,r3:2)
181181
define <4 x i16> @test_15(<4 x i16> %a0, <4 x i16> %a1) #0 {
182182
%v0 = icmp uge <4 x i16> %a0, %a1
183183
%v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
@@ -193,7 +193,7 @@ define <2 x i32> @test_16(<2 x i32> %a0, <2 x i32> %a1) #0 {
193193
}
194194

195195
; CHECK-LABEL: test_17:
196-
; CHECK: r1:0 = vmaxuw(r3:2,r1:0)
196+
; CHECK: r1:0 = vmaxuw(r1:0,r3:2)
197197
define <2 x i32> @test_17(<2 x i32> %a0, <2 x i32> %a1) #0 {
198198
%v0 = icmp uge <2 x i32> %a0, %a1
199199
%v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1

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