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iclsrc
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Merge from 'sycl' to 'sycl-web' (#3)
2 parents afda5ef + e1e3962 commit b474e0c

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‎buildbot/dependency.conf

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
[VERSIONS]
2-
# https://github.com/intel/llvm/releases/download/2020-WW36/oclcpuexp-2020.11.8.0.27_rel.tar.gz
3-
ocl_cpu_rt_ver=2020.11.8.0.27
4-
# https://github.com/intel/llvm/releases/download/2020-WW36/win-oclcpuexp-2020.11.8.0.27_rel.zip
5-
ocl_cpu_rt_ver_win=2020.11.8.0.27
2+
# https://github.com/intel/llvm/releases/download/2020-WW41/oclcpuexp-2020.11.10.0.05_rel.tar.gz
3+
ocl_cpu_rt_ver=2020.11.10.0.05
4+
# https://github.com/intel/llvm/releases/download/2020-WW41/win-oclcpuexp-2020.11.10.0.05_rel.zip
5+
ocl_cpu_rt_ver_win=2020.11.10.0.05
66
# Same GPU driver supports Level Zero and OpenCL:
77
# https://github.com/intel/compute-runtime/releases/tag/20.39.17972
88
ocl_gpu_rt_ver=20.39.17972
@@ -11,23 +11,23 @@ ocl_gpu_rt_ver=20.39.17972
1111
ocl_gpu_rt_ver_win=27.20.100.8778
1212
intel_sycl_ver=build
1313
# https://github.com/oneapi-src/oneTBB/releases/download/v2021.1-beta08/oneapi-tbb-2021.1-beta08-lin.tgz
14-
tbb_ver=2021.1.9.636
14+
tbb_ver=2021.1.10.2267
1515
# https://github.com/oneapi-src/oneTBB/releases/download/v2021.1-beta08/oneapi-tbb-2021.1-beta08-win.zip
16-
tbb_ver_win=2021.1.9.636
17-
# https://github.com/intel/llvm/releases/download/2020-WW36/fpgaemu-2020.11.8.0.27_rel.tar.gz
18-
ocl_fpga_emu_ver=2020.11.8.0.27
19-
# https://github.com/intel/llvm/releases/download/2020-WW36/win-fpgaemu-2020.11.8.0.27_rel.zip
20-
ocl_fpga_emu_ver_win=2020.11.8.0.27
21-
fpga_ver=20200811_000001
22-
fpga_ver_win=20200811_000006
16+
tbb_ver_win=2021.1.10.2267
17+
# https://github.com/intel/llvm/releases/download/2020-WW41/fpgaemu-2020.11.10.0.05_rel.tar.gz
18+
ocl_fpga_emu_ver=2020.11.10.0.05
19+
# https://github.com/intel/llvm/releases/download/2020-WW41/win-fpgaemu-2020.11.10.0.05_rel.zip
20+
ocl_fpga_emu_ver_win=2020.11.10.0.05
21+
fpga_ver=20200913_000017
22+
fpga_ver_win=20200913_000017
2323

2424
[DRIVER VERSIONS]
25-
cpu_driver_lin=2020.11.8.0.27
26-
cpu_driver_win=2020.11.8.0.27
25+
cpu_driver_lin=2020.11.10.0.05
26+
cpu_driver_win=2020.11.10.0.05
2727
gpu_driver_lin=20.39.17972
2828
gpu_driver_win=27.20.100.8778
29-
fpga_driver_lin=2020.11.8.0.27
30-
fpga_driver_win=2020.11.8.0.27
29+
fpga_driver_lin=2020.11.10.0.05
30+
fpga_driver_win=2020.11.10.0.05
3131
# NVidia CUDA driver
3232
# TODO provide URL for CUDA driver
3333
nvidia_gpu_driver_lin=435.21

‎sycl/include/CL/sycl/half_type.hpp

Lines changed: 16 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -220,15 +220,12 @@ inline float cast_if_host_half(half_impl::half val) {
220220
} // namespace sycl
221221
} // __SYCL_INLINE_NAMESPACE(cl)
222222

223-
using half = cl::sycl::detail::half_impl::half;
224-
225223
// Partial specialization of some functions in namespace `std`
226224
namespace std {
227225

228-
229226
// Partial specialization of `std::hash<cl::sycl::half>`
230-
template <> struct hash<half> {
231-
size_t operator()(half const &Key) const noexcept {
227+
template <> struct hash<cl::sycl::half> {
228+
size_t operator()(cl::sycl::half const &Key) const noexcept {
232229
return hash<uint16_t>{}(reinterpret_cast<const uint16_t &>(Key));
233230
}
234231
};
@@ -260,7 +257,7 @@ template <> struct hash<half> {
260257

261258
#define SYCL_HLF_RADIX 2
262259

263-
template <> struct numeric_limits<half> {
260+
template <> struct numeric_limits<cl::sycl::half> {
264261
static constexpr const bool is_specialized = true;
265262

266263
static constexpr const bool is_signed = true;
@@ -307,51 +304,53 @@ template <> struct numeric_limits<half> {
307304

308305
static constexpr const float_round_style round_style = round_to_nearest;
309306

310-
static __SYCL_CONSTEXPR_ON_DEVICE const half(min)() noexcept {
307+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half(min)() noexcept {
311308
return SYCL_HLF_MIN;
312309
}
313310

314-
static __SYCL_CONSTEXPR_ON_DEVICE const half(max)() noexcept {
311+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half(max)() noexcept {
315312
return SYCL_HLF_MAX;
316313
}
317314

318-
static __SYCL_CONSTEXPR_ON_DEVICE const half lowest() noexcept {
315+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half lowest() noexcept {
319316
return -SYCL_HLF_MAX;
320317
}
321318

322-
static __SYCL_CONSTEXPR_ON_DEVICE const half epsilon() noexcept {
319+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half epsilon() noexcept {
323320
return SYCL_HLF_EPSILON;
324321
}
325322

326-
static __SYCL_CONSTEXPR_ON_DEVICE const half round_error() noexcept {
323+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half
324+
round_error() noexcept {
327325
return 0.5F;
328326
}
329327

330-
static __SYCL_CONSTEXPR_ON_DEVICE const half infinity() noexcept {
328+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half infinity() noexcept {
331329
return __builtin_huge_valf();
332330
}
333331

334-
static __SYCL_CONSTEXPR_ON_DEVICE const half quiet_NaN() noexcept {
332+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half quiet_NaN() noexcept {
335333
return __builtin_nanf("");
336334
}
337335

338-
static __SYCL_CONSTEXPR_ON_DEVICE const half signaling_NaN() noexcept {
336+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half
337+
signaling_NaN() noexcept {
339338
return __builtin_nansf("");
340339
}
341340

342-
static __SYCL_CONSTEXPR_ON_DEVICE const half denorm_min() noexcept {
341+
static __SYCL_CONSTEXPR_ON_DEVICE const cl::sycl::half denorm_min() noexcept {
343342
return 5.96046e-08F;
344343
}
345344
};
346345

347346
} // namespace std
348347

349-
inline std::ostream &operator<<(std::ostream &O, half const &rhs) {
348+
inline std::ostream &operator<<(std::ostream &O, cl::sycl::half const &rhs) {
350349
O << static_cast<float>(rhs);
351350
return O;
352351
}
353352

354-
inline std::istream &operator>>(std::istream &I, half &rhs) {
353+
inline std::istream &operator>>(std::istream &I, cl::sycl::half &rhs) {
355354
float ValFloat = 0.0f;
356355
I >> ValFloat;
357356
rhs = ValFloat;

‎sycl/test/basic_tests/buffer/buffer.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -579,7 +579,8 @@ int main() {
579579

580580
{
581581
std::allocator<float8> buf_alloc;
582-
cl::sycl::shared_ptr_class<float8> data(new float8[8]);
582+
cl::sycl::shared_ptr_class<float8> data(new float8[8],
583+
[](float8 *p) { delete[] p; });
583584
cl::sycl::buffer<float8, 1, std::allocator<float8>>
584585
b(data, cl::sycl::range<1>(8), buf_alloc);
585586
}

‎sycl/test/reduction/reduction_usm.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
// XFAIL: accelerator
21
// UNSUPPORTED: cuda
32
// Reductions use work-group builtins not yet supported by CUDA.
43

‎sycl/test/sub_group/broadcast.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
// XFAIL: cpu
21
// UNSUPPORTED: cuda
32
// CUDA compilation and runtime do not yet support sub-groups.
43

‎sycl/test/sub_group/broadcast_fp64.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
// XFAIL: cpu
21
// UNSUPPORTED: cuda
32
// CUDA compilation and runtime do not yet support sub-groups.
43

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