Updated vc-intrinsics version to match llvm change 1da09b7

Author: DenisBakhvalov

llvm/lib/SYCLLowerIR/CMakeLists.txt

@@ -7,7 +7,7 @@ if (NOT TARGET LLVMGenXIntrinsics)
     include(FetchContent)
     FetchContent_Declare(vc-intrinsics
       GIT_REPOSITORY https://github.com/intel/vc-intrinsics.git
-      GIT_TAG        5e35898100ebe3747ea50c91b05e679757b25703
+      GIT_TAG        91f3df2cd87a7b9706df32046c34fe8d07ecf854
     )
     FetchContent_MakeAvailable(vc-intrinsics)
     FetchContent_GetProperties(vc-intrinsics)

llvm/test/SYCLLowerIR/esimd_lower_intrins.ll

@@ -52,15 +52,15 @@ define dso_local spir_func <32 x i32>  @FUNC_3() !sycl_explicit_simd !1 {
 
 define dso_local spir_func <32 x i32>  @FUNC_4() !sycl_explicit_simd !1 {
   %ret_val = call spir_func  <32 x i32>  @_Z33__esimd_flat_block_read_unalignedIjLi32ELN2cm3gen9CacheHintE0ELS2_0EENS1_13__vector_typeIT_XT0_EE4typeEy(i64 0)
-; CHECK: %{{[0-9a-zA-Z_.]+}} = call <32 x i32> @llvm.genx.svm.block.ld.unaligned.v32i32(i64 0)
+; CHECK: %{{[0-9a-zA-Z_.]+}} = call <32 x i32> @llvm.genx.svm.block.ld.unaligned.v32i32.i64(i64 0)
   ret <32 x i32>  %ret_val
 }
 
 define dso_local spir_func void  @FUNC_5() !sycl_explicit_simd !1 {
   %a_1 = alloca  <32 x i32>
   %1 = load  <32 x i32>,  <32 x i32>* %a_1
   call spir_func  void  @_Z24__esimd_flat_block_writeIjLi32ELN2cm3gen9CacheHintE0ELS2_0EEvyNS1_13__vector_typeIT_XT0_EE4typeE(i64 0,  <32 x i32> %1)
-; CHECK: call void @llvm.genx.svm.block.st.v32i32(i64 0, <32 x i32> %{{[0-9a-zA-Z_.]+}})
+; CHECK: call void @llvm.genx.svm.block.st.i64.v32i32(i64 0, <32 x i32> %{{[0-9a-zA-Z_.]+}})
   ret void
 }
 

sycl/test/esimd/intrins_trans.cpp

@@ -57,9 +57,9 @@ SYCL_ESIMD_FUNCTION SYCL_EXTERNAL simd<float, 16> foo() {
   uintptr_t addr = reinterpret_cast<uintptr_t>(ptr);
   simd<uint32_t, VL> v00 =
       __esimd_flat_block_read_unaligned<uint32_t, VL>(addr);
-  // CHECK: %{{[0-9a-zA-Z_.]+}} = call <32 x i32> @llvm.genx.svm.block.ld.unaligned.v32i32(i64 %{{[0-9a-zA-Z_.]+}})
+  // CHECK: %{{[0-9a-zA-Z_.]+}} = call <32 x i32> @llvm.genx.svm.block.ld.unaligned.v32i32.i64(i64 %{{[0-9a-zA-Z_.]+}})
   __esimd_flat_block_write<uint32_t, VL>(addr, v00.data());
-  // CHECK: call void @llvm.genx.svm.block.st.v32i32(i64 %{{[0-9a-zA-Z_.]+}}, <32 x i32> %{{[0-9a-zA-Z_.]+}})
+  // CHECK: call void @llvm.genx.svm.block.st.i64.v32i32(i64 %{{[0-9a-zA-Z_.]+}}, <32 x i32> %{{[0-9a-zA-Z_.]+}})
 
   simd<uint32_t, VL> v01 =
       __esimd_flat_read<uint32_t, VL>(v_addr.data(), 0, pred.data());