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iclsrc
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Merge from 'sycl' to 'sycl-web'
2 parents 509e671 + 0ddb9fe commit db465f5

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16 files changed

+150
-22
lines changed

16 files changed

+150
-22
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‎clang/include/clang/Driver/Options.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1830,6 +1830,9 @@ def fstrict_vtable_pointers: Flag<["-"], "fstrict-vtable-pointers">,
18301830
def fstrict_overflow : Flag<["-"], "fstrict-overflow">, Group<f_Group>;
18311831
def fintelfpga : Flag<["-"], "fintelfpga">, Group<f_Group>,
18321832
Flags<[CC1Option, CoreOption]>, HelpText<"Perform ahead of time compilation for FPGA">;
1833+
def fsycl_enable_usm_address_spaces : Flag<["-"], "fsycl-enable-usm-address-spaces">,
1834+
Group<f_Group>, Flags<[CC1Option, CoreOption]>,
1835+
HelpText<"Enable SPV_INTEL_usm_storage_classes extension">;
18331836
def fsycl_device_only : Flag<["-"], "fsycl-device-only">, Flags<[CoreOption]>,
18341837
HelpText<"Compile SYCL kernels for device">;
18351838
def fsycl_targets_EQ : CommaJoined<["-"], "fsycl-targets=">, Flags<[DriverOption, CC1Option, CoreOption]>,

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7622,7 +7622,17 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
76227622
TranslatorArgs.push_back(Output.getFilename());
76237623
if (getToolChain().getTriple().isSYCLDeviceEnvironment()) {
76247624
TranslatorArgs.push_back("-spirv-max-version=1.1");
7625-
TranslatorArgs.push_back("-spirv-ext=+all");
7625+
std::string ExtArg("-spirv-ext=+all");
7626+
// Disable SPV_INTEL_usm_storage_classes by default since it adds new
7627+
// storage classes that represent global_device and global_host address
7628+
// spaces, which are not supported for all targets. With the extension
7629+
// disable the storage classes will be lowered to CrossWorkgroup storage
7630+
// class that is mapped to just global address space.
7631+
if (!(getToolChain().getTriple().getSubArch() ==
7632+
llvm::Triple::SPIRSubArch_fpga &&
7633+
TCArgs.hasArg(options::OPT_fsycl_enable_usm_address_spaces)))
7634+
ExtArg += ",-SPV_INTEL_usm_storage_classes";
7635+
TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg));
76267636
}
76277637
for (auto I : Inputs) {
76287638
std::string Filename(I.getFilename());

‎clang/test/Driver/sycl-offload-intelfpga.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232
// CHK-FPGA-LINK-NOT: clang-offload-bundler{{.*}}
3333
// CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
3434
// CHK-FPGA-LINK: sycl-post-link{{.*}} "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
35-
// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2]]"
35+
// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
3636
// CHK-FPGA-EARLY: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
3737
// CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocx]]" "[[OUTPUT3]]" "-sycl"
3838
// CHK-FPGA-LINK: llvm-ar{{.*}} "cr" "libfoo.a" "[[INPUT]]"
@@ -58,7 +58,7 @@
5858
// CHK-FPGA-LINK-WIN-NOT: clang-offload-bundler{{.*}}
5959
// CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
6060
// CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
61-
// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2]]"
61+
// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
6262
// CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
6363
// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[INPUT]]" {{.*}} "-OUT:libfoo.lib"
6464

@@ -112,7 +112,7 @@
112112
// CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]]" "-unbundle"
113113
// CHK-FPGA: llvm-no-spir-kernel{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT3:.+\.o]]"
114114
// CHK-FPGA: llvm-link{{.*}} "[[OUTPUT3]]" "-o" "[[OUTPUT4:.+\.bc]]"
115-
// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT4]]"
115+
// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT4]]"
116116
// CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT6:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "[[OUTPUT5]]"
117117
// CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK3:.+\.o]]" "[[OUTPUT6]]"
118118
// CHK-FPGA: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" {{.*}} "-outputs=[[FINALLINK4:.+\.txt]]" "-unbundle"

‎clang/test/Driver/sycl-offload.c

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -639,17 +639,28 @@
639639

640640
/// Ahead of Time compilation for fpga, gen, cpu - tool invocation
641641
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s -### 2>&1 \
642-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA
642+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
643643
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %s -### 2>&1 \
644-
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA
644+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE
645+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \
646+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
647+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -fsycl-enable-usm-address-spaces %s -### 2>&1 \
648+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE
649+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \
650+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN
651+
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \
652+
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-CPU
645653
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \
646654
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN
647655
// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s -### 2>&1 \
648656
// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-CPU
649657
// CHK-TOOLS-AOT: clang{{.*}} "-fsycl-is-device" {{.*}} "-o" "[[OUTPUT1:.+\.bc]]"
650658
// CHK-TOOLS-AOT: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2:.+\.bc]]"
651659
// CHK-TOOLS-AOT: sycl-post-link{{.*}} "-o" "[[OUTPUT2_1:.+\.bc]]" "[[OUTPUT2]]"
652-
// CHK-TOOLS-AOT: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2_1]]"
660+
// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]"
661+
// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]"
662+
// CHK-TOOLS-FPGA-USM-DISABLE: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]"
663+
// CHK-TOOLS-FPGA-USM-ENABLE: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2_1]]"
653664
// CHK-TOOLS-FPGA: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]"
654665
// CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]"
655666
// CHK-TOOLS-CPU: opencl-aot{{.*}} "-o=[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]"

‎clang/test/Driver/sycl.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,11 @@
4040
// DEFAULT: "-triple" "spir64-unknown-{{.*}}-sycldevice{{.*}}" "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
4141
// DEFAULT: "-internal-isystem" "{{.*}}bin{{[/\\]+}}..{{[/\\]+}}include{{[/\\]+}}sycl"
4242
// DEFAULT: "-internal-isystem" "{{.*lib.*clang.*include}}"
43-
// DEFAULT-NOT: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all"
43+
// DEFAULT-NOT: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes"
4444
// DEFAULT-NOT: "-std=c++11"
4545
// DEFAULT-NOT: "-std=c++14"
4646
// NO-BITCODE: "-triple" "spir64-unknown-{{.*}}-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
47-
// NO-BITCODE: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all"
47+
// NO-BITCODE: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes"
4848
// TARGET: "-triple" "spir64-unknown-linux-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
4949
// COMBINED: "-triple" "spir64-unknown-{{.*}}-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc"
5050
// TEXTUAL: "-triple" "spir64-unknown-{{.*}}-sycldevice{{.*}}" "-fsycl-is-device"{{.*}} "-emit-llvm"

‎sycl/include/CL/__spirv/spirv_ops.hpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,15 @@ __SYCL_CONVERGENT__ extern SYCL_EXTERNAL void
205205
__spirv_SubgroupBlockWriteINTEL(__attribute__((opencl_global)) uint32_t *Ptr,
206206
dataT Data) noexcept;
207207

208+
template <typename dataT>
209+
__SYCL_CONVERGENT__ extern SYCL_EXTERNAL dataT __spirv_SubgroupBlockReadINTEL(
210+
const __attribute__((opencl_global)) uint64_t *Ptr) noexcept;
211+
212+
template <typename dataT>
213+
__SYCL_CONVERGENT__ extern SYCL_EXTERNAL void
214+
__spirv_SubgroupBlockWriteINTEL(__attribute__((opencl_global)) uint64_t *Ptr,
215+
dataT Data) noexcept;
216+
208217
template <typename dataT>
209218
extern SYCL_EXTERNAL int32_t __spirv_ReadPipe(RPipeTy<dataT> Pipe, dataT *Data,
210219
int32_t Size,

‎sycl/include/CL/sycl/backend_types.hpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,34 @@
1010

1111
#include <CL/sycl/detail/defines.hpp>
1212

13+
#include <fstream>
14+
#include <iostream>
15+
#include <istream>
16+
#include <string>
17+
1318
__SYCL_INLINE_NAMESPACE(cl) {
1419
namespace sycl {
1520

1621
enum class backend : char { host, opencl, level0, cuda };
1722

1823
template <backend name, typename SYCLObjectT> struct interop;
1924

25+
inline std::ostream &operator<<(std::ostream &Out, backend be) {
26+
switch (be) {
27+
case backend::host:
28+
Out << std::string("host");
29+
break;
30+
case backend::opencl:
31+
Out << std::string("opencl");
32+
break;
33+
case backend::level0:
34+
Out << std::string("level-zero");
35+
break;
36+
case backend::cuda:
37+
Out << std::string("cuda");
38+
}
39+
return Out;
40+
}
41+
2042
} // namespace sycl
2143
} // __SYCL_INLINE_NAMESPACE(cl)

‎sycl/include/CL/sycl/detail/generic_type_traits.hpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -367,12 +367,12 @@ using select_apply_cl_scalar_t =
367367

368368
// Shortcuts for selecting scalar int/unsigned int/fp type.
369369
template <typename T>
370-
using select_cl_scalar_intergal_signed_t =
370+
using select_cl_scalar_integral_signed_t =
371371
select_apply_cl_scalar_t<T, sycl::cl_char, sycl::cl_short, sycl::cl_int,
372372
sycl::cl_long>;
373373

374374
template <typename T>
375-
using select_cl_scalar_intergal_unsigned_t =
375+
using select_cl_scalar_integral_unsigned_t =
376376
select_apply_cl_scalar_t<T, sycl::cl_uchar, sycl::cl_ushort, sycl::cl_uint,
377377
sycl::cl_ulong>;
378378

@@ -382,16 +382,16 @@ using select_cl_scalar_float_t =
382382
sycl::cl_double>;
383383

384384
template <typename T>
385-
using select_cl_scalar_intergal_t =
385+
using select_cl_scalar_integral_t =
386386
conditional_t<std::is_signed<T>::value,
387-
select_cl_scalar_intergal_signed_t<T>,
388-
select_cl_scalar_intergal_unsigned_t<T>>;
387+
select_cl_scalar_integral_signed_t<T>,
388+
select_cl_scalar_integral_unsigned_t<T>>;
389389

390390
// select_cl_scalar_t picks corresponding cl_* type for input
391391
// scalar T or returns T if T is not scalar.
392392
template <typename T>
393393
using select_cl_scalar_t = conditional_t<
394-
std::is_integral<T>::value, select_cl_scalar_intergal_t<T>,
394+
std::is_integral<T>::value, select_cl_scalar_integral_t<T>,
395395
conditional_t<
396396
std::is_floating_point<T>::value, select_cl_scalar_float_t<T>,
397397
// half is a special case: it is implemented differently on host and

‎sycl/include/CL/sycl/intel/sub_group.hpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -55,11 +55,9 @@ __SYCL_SG_GENERATE_BODY_2ARG(shuffle_up, SubgroupShuffleUpINTEL)
5555

5656
#undef __SYCL_SG_GENERATE_BODY_2ARG
5757

58-
// Selects 8-bit, 16-bit or 32-bit type depending on size of T. If T doesn't
59-
// maps to mentioned types, then void is returned
58+
// Selects 8, 16, 32, or 64-bit type depending on size of scalar type T.
6059
template <typename T>
61-
using SelectBlockT =
62-
select_apply_cl_scalar_t<T, uint8_t, uint16_t, uint32_t, void>;
60+
using SelectBlockT = select_cl_scalar_integral_unsigned_t<T>;
6361

6462
template <typename T, access::address_space Space>
6563
using AcceptableForGlobalLoadStore =

‎sycl/include/CL/sycl/platform.hpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,11 @@ class __SYCL_EXPORT platform {
102102
/// \return a vector of all available SYCL platforms.
103103
static vector_class<platform> get_platforms();
104104

105+
/// Returns the backend associated with this platform.
106+
///
107+
/// \return the backend associated with this platform
108+
backend get_backend() const noexcept;
109+
105110
/// Gets the native handle of the SYCL platform.
106111
///
107112
/// \return a native handle, the type of which defined by the backend.

‎sycl/plugins/cuda/pi_cuda.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -276,9 +276,12 @@ _pi_event::_pi_event(pi_command_type type, pi_context context, pi_queue queue)
276276

277277
assert(type != PI_COMMAND_TYPE_USER);
278278

279-
PI_CHECK_ERROR(cuEventCreate(&evEnd_, CU_EVENT_DEFAULT));
279+
bool profilingEnabled = queue_->properties_ & PI_QUEUE_PROFILING_ENABLE;
280280

281-
if (queue_->properties_ & PI_QUEUE_PROFILING_ENABLE) {
281+
PI_CHECK_ERROR(cuEventCreate(
282+
&evEnd_, profilingEnabled ? CU_EVENT_DEFAULT : CU_EVENT_DISABLE_TIMING));
283+
284+
if (profilingEnabled) {
282285
PI_CHECK_ERROR(cuEventCreate(&evQueued_, CU_EVENT_DEFAULT));
283286
PI_CHECK_ERROR(cuEventCreate(&evStart_, CU_EVENT_DEFAULT));
284287
}

‎sycl/source/detail/platform_impl.hpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,9 @@ class platform_impl {
106106
/// \return a vector of all available SYCL platforms.
107107
static vector_class<platform> get_platforms();
108108

109+
// \return the Backend associated with this platform.
110+
backend get_backend() const noexcept { return getPlugin().getBackend(); }
111+
109112
// \return the Plugin associated with this platform.
110113
const plugin &getPlugin() const {
111114
assert(!MHostPlatform && "Plugin is not available for Host.");

‎sycl/source/platform.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,8 @@ vector_class<platform> platform::get_platforms() {
4343
return detail::platform_impl::get_platforms();
4444
}
4545

46+
backend platform::get_backend() const noexcept { return impl->get_backend(); }
47+
4648
template <info::platform param>
4749
typename info::param_traits<info::platform, param>::return_type
4850
platform::get_info() const {

‎sycl/test/abi/sycl_symbols_linux.dump

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3523,6 +3523,7 @@ _ZNK2cl4sycl7sampler19get_addressing_modeEv
35233523
_ZNK2cl4sycl7sampler33get_coordinate_normalization_modeEv
35243524
_ZNK2cl4sycl7samplereqERKS1_
35253525
_ZNK2cl4sycl7samplerneERKS1_
3526+
_ZNK2cl4sycl8platform11get_backendEv
35263527
_ZNK2cl4sycl8platform11get_devicesENS0_4info11device_typeE
35273528
_ZNK2cl4sycl8platform13has_extensionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
35283529
_ZNK2cl4sycl8platform3getEv

‎sycl/test/basic_tests/get_backend.cpp

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
// RUN: %clangxx -fsycl %s -o %t.out
2+
// RUN: %t.out
3+
//
4+
//==----------------- get_backend.cpp ------------------------==//
5+
// This is a test of get_backend().
6+
// Also prints handy info about the system.
7+
// Do not set SYCL_BE. We do not want the preferred backend.
8+
//==----------------------------------------------------------==//
9+
10+
#include <CL/sycl.hpp>
11+
#include <CL/sycl/backend_types.hpp>
12+
#include <iostream>
13+
14+
using namespace cl::sycl;
15+
16+
bool check(backend be) {
17+
switch (be) {
18+
case backend::opencl:
19+
case backend::level0:
20+
case backend::cuda:
21+
case backend::host:
22+
return true;
23+
default:
24+
return false;
25+
}
26+
return false;
27+
}
28+
29+
int main() {
30+
for (const auto &plt : platform::get_platforms()) {
31+
if (!plt.is_host()) {
32+
if (check(plt.get_backend()) == false) {
33+
std::cout << "Failed" << std::endl;
34+
return 1;
35+
}
36+
}
37+
}
38+
std::cout << "Passed" << std::endl;
39+
return 0;
40+
}

‎sycl/test/sub_group/load_store.cpp

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,8 @@ template <typename T> void check(queue &Queue) {
158158
int main() {
159159
queue Queue;
160160
if (!Queue.get_device().has_extension("cl_intel_subgroups") &&
161-
!Queue.get_device().has_extension("cl_intel_subgroups_short")) {
161+
!Queue.get_device().has_extension("cl_intel_subgroups_short") &&
162+
!Queue.get_device().has_extension("cl_intel_subgroups_long")) {
162163
std::cout << "Skipping test\n";
163164
return 0;
164165
}
@@ -200,6 +201,26 @@ int main() {
200201
check<aligned_half, 8>(Queue);
201202
}
202203
}
204+
if (Queue.get_device().has_extension("cl_intel_subgroups_long")) {
205+
typedef long aligned_long __attribute__((aligned(16)));
206+
check<aligned_long>(Queue);
207+
check<aligned_long, 1>(Queue);
208+
check<aligned_long, 2>(Queue);
209+
check<aligned_long, 4>(Queue);
210+
check<aligned_long, 8>(Queue);
211+
typedef unsigned long aligned_ulong __attribute__((aligned(16)));
212+
check<aligned_ulong>(Queue);
213+
check<aligned_ulong, 1>(Queue);
214+
check<aligned_ulong, 2>(Queue);
215+
check<aligned_ulong, 4>(Queue);
216+
check<aligned_ulong, 8>(Queue);
217+
typedef double aligned_double __attribute__((aligned(16)));
218+
check<aligned_double>(Queue);
219+
check<aligned_double, 1>(Queue);
220+
check<aligned_double, 2>(Queue);
221+
check<aligned_double, 4>(Queue);
222+
check<aligned_double, 8>(Queue);
223+
}
203224
std::cout << "Test passed." << std::endl;
204225
return 0;
205226
}

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