Merge from 'sycl' to 'sycl-web'

Author: iclsrc

.github/CODEOWNERS

@@ -8,7 +8,7 @@ llvm-spirv/ @AlexeySotkin @AlexeySachkov
 
 opencl-aot/ @dm-vodopyanov @AlexeySachkov @romanovvlad
 
-libdevice/ @asavonic @vzakhari
+libdevice/ @vzakhari
 
 sycl/ @intel/llvm-reviewers-runtime
 

CONTRIBUTING.md

@@ -20,6 +20,11 @@ is strongly encouraged that you submit the patch to https://llvm.org/ directly.
 See [LLVM contribution guidelines](https://llvm.org/docs/Contributing.html)
 for more information.
 
+**NB**: A change in compiler and runtime should be accompanied with
+corresponding test changes.
+See [Test DPC++ toolchain](sycl/doc/GetStartedGuide.md#test-dpc-toolchain)
+section of Get Started guide for more information.
+
 **Note (October, 2020)**: DPC++ runtime and compiler ABI is currently in frozen
 state. This means that no ABI-breaking changes will be accepted by default.
 Project maintainers may still approve breaking changes in some cases. Please,

buildbot/dependency.conf

@@ -4,8 +4,8 @@ ocl_cpu_rt_ver=2020.11.11.0.04
 # https://github.com/intel/llvm/releases/download/2020-WW45/win-oclcpuexp-2020.11.11.0.04_rel.zip
 ocl_cpu_rt_ver_win=2020.11.11.0.04
 # Same GPU driver supports Level Zero and OpenCL:
-# https://github.com/intel/compute-runtime/releases/tag/20.44.18297
-ocl_gpu_rt_ver=20.44.18297
+# https://github.com/intel/compute-runtime/releases/tag/20.45.18403
+ocl_gpu_rt_ver=20.45.18403
 # Same GPU driver supports Level Zero and OpenCL:
 # https://downloadmirror.intel.com/29988/a08/igfx_win10_100.8935.zip
 ocl_gpu_rt_ver_win=27.20.100.8935
@@ -24,7 +24,7 @@ fpga_ver_win=20201022_000005
 [DRIVER VERSIONS]
 cpu_driver_lin=2020.11.11.0.04
 cpu_driver_win=2020.11.11.0.04
-gpu_driver_lin=20.44.18297
+gpu_driver_lin=20.45.18403
 gpu_driver_win=27.20.100.8935
 fpga_driver_lin=2020.11.11.0.04
 fpga_driver_win=2020.11.11.0.04

clang/include/clang/Basic/AttrDocs.td

@@ -2397,6 +2397,22 @@ is unspecified and is therefore considered infinite.
 In case of ivdep being applied both w/o an array variable and for a particular
 array, the array variables that were not designated a separate ivdep will receive
 the no-array ivdep's safelen, with the correspondent treatment by the backend.
+
+.. code-block:: c++
+
+  void foo() {
+    int a[10];
+    [[intel::ivdep]] for (int i = 0; i != 10; ++i) { }
+    [[intel::ivdep(2)]] for (int i = 0; i != 10; ++i) { }
+    [[intel::ivdep(a)]] for (int i = 0; i != 10; ++i) { }
+    [[intel::ivdep(a, 2)]] for (int i = 0; i != 10; ++i) { }
+  }
+
+  template<int N>
+  void bar() {
+    [[intel::ivdep(N)]] for(;;) { }
+  }
+
   }];
 }
 
@@ -2407,6 +2423,19 @@ def SYCLIntelFPGAIIAttrDocs : Documentation {
 This attribute applies to a loop. Indicates that the loop should be pipelined
 with an initiation interval of N. N must be a positive integer. Cannot be
 applied multiple times to the same loop.
+
+.. code-block:: c++
+
+  void foo() {
+    int var = 0;
+    [[intel::ii(4)]] for (int i = 0; i < 10; ++i) var++;
+  }
+
+  template<int N>
+  void bar() {
+    [[intel::ii(N)]] for(;;) { }
+  }
+
   }];
 }
 
@@ -2418,6 +2447,19 @@ This attribute applies to a loop. Indicates that the loop should allow no more
 than N threads or iterations to execute it simultaneously. N must be a non
 negative integer. '0' indicates the max_concurrency case to be unbounded. Cannot
 be applied multiple times to the same loop.
+
+.. code-block:: c++
+
+  void foo() {
+    int a[10];
+    [[intel::max_concurrency(2)]] for (int i = 0; i != 10; ++i) a[i] = 0;
+  }
+
+  template<int N>
+  void bar() {
+    [[intel::max_concurrency(N)]] for(;;) { }
+  }
+
   }];
 }
 
@@ -2429,6 +2471,34 @@ This attribute applies to a loop. Indicates that the loop nest should be
 coalesced into a single loop without affecting functionality. Parameter N is
 optional. If specified, it shall be a positive integer, and indicates how many
 of the nested loop levels should be coalesced.
+
+.. code-block:: c++
+
+  void foo() {
+    int a[10];
+    [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) a[i] = 0;
+  }
+
+  template<int N>
+  void loop_coalesce() {
+    int j = 0, n = 48;
+    [[intel::loop_coalesce(N)]]
+    while (j < n) {
+      if (j % 4) {
+        ++j;
+        continue;
+      }
+    }
+    j = 0;
+    [[intel::loop_coalesce]]
+    while (j < n) {
+      if (j % 6) {
+        ++j;
+        continue;
+      }
+    }
+  }
+
   }];
 }
 
@@ -2440,6 +2510,14 @@ This attribute applies to a loop. Disables pipelining of the loop data path,
 causing the loop to be executed serially. Cannot be used on the same loop in
 conjunction with max_interleaving, speculated_iterations, max_concurrency, ii
 or ivdep.
+
+.. code-block:: c++
+
+  void foo() {
+    int var = 0;
+    [[intel::disable_loop_pipelining] for (int i = 0; i < 10; ++i) var++;
+  }
+
   }];
 }
 
@@ -2453,6 +2531,19 @@ mean that this attribute can only be applied to inner loops in user code - outer
 loops in user code may still be contained in an implicit loop due to NDRange).
 Parameter N is mandatory, and shall be non-negative integer. Cannot be
 used on the same loop in conjunction with disable_loop_pipelining.
+
+.. code-block:: c++
+
+  void foo() {
+    int a[10];
+    [[intel::max_interleaving(4)]] for (int i = 0; i != 10; ++i) a[i] = 0;
+  }
+
+  template<int N>
+  void bar() {
+    [[intel::max_interleaving(N)]] for(;;) { }
+  }
+
   }];
 }
 
@@ -2465,6 +2556,19 @@ iterations that will be in flight for a loop invocation (i.e. the exit
 condition for these iterations will not have been evaluated yet).
 Parameter N is mandatory, and may either be 0, or a positive integer. Cannot be
 used on the same loop in conjunction with disable_loop_pipelining.
+
+.. code-block:: c++
+
+  void foo() {
+    int var = 0;
+    [[intel::speculated_iterations(4)]] for (int i = 0; i < 10; ++i) var++;
+  }
+
+  template<int N>
+  void bar() {
+    [[intel::speculated_iterations(N)]] for(;;) { }
+  }
+
   }];
 }
 
@@ -2474,6 +2578,21 @@ def SYCLIntelFPGANofusionAttrDocs : Documentation {
   let Content = [{
 This attribute applies to a loop. Indicates that the annotated
 loop should not be fused with any adjacent loop.
+
+.. code-block:: c++
+
+  void foo() {
+    [[intel::nofusion]] for (int i=0; i<10;++i) { }
+  }
+
+  void nofusion() {
+    int a1[10];
+    for (int i = 0; i < 10; ++i) {
+    [[intel::nofusion]] for (int j = 0; j < 10; ++j) {
+      a1[i] += a1[j];
+    }
+  }
+
   }];
 }
 

sycl/doc/GetStartedGuide.md

@@ -218,7 +218,7 @@ folder:
       /opt/intel/oclfpgaemu_<fpga_version>/x64
     ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbbmalloc.so
       /opt/intel/oclfpgaemu_<fpga_version>/x64
-    ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbb.so.2
+    ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbb.so.12
       /opt/intel/oclfpgaemu_<fpga_version>/x64
     ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbbmalloc.so.2
       /opt/intel/oclfpgaemu_<fpga_version>/x64
@@ -227,7 +227,7 @@ folder:
       /opt/intel/oclcpuexp_<cpu_version>/x64
     ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbbmalloc.so
       /opt/intel/oclcpuexp_<cpu_version>/x64
-    ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbb.so.2
+    ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbb.so.12
       /opt/intel/oclcpuexp_<cpu_version>/x64
     ln -s /opt/intel/tbb_<tbb_version>/tbb/lib/intel64/gcc4.8/libtbbmalloc.so.2
       /opt/intel/oclcpuexp_<cpu_version>/x64
@@ -280,7 +280,40 @@ command:
 
 ### Test DPC++ toolchain
 
-#### Run regression tests
+Every product change should be accompanied with corresponding test modification
+(adding new test(s), extending, removing or modifying existing test(s)).
+
+There are 3 types of tests which are used for DPC++ toolchain validation:
+* DPC++ in-tree LIT tests including [check-llvm](../../llvm/test),
+[check-clang](../../clang/test), [check-llvm-spirv](../../llvm-spirv/test) and
+[check-sycl](../../sycl/test) targets stored in this repository. These tests
+should not have hardware (e.g. GPU, FPGA, etc.) or external software
+dependencies (e.g. OpenCL, Level Zero, CUDA runtimes). All tests not following
+this approach should be moved to DPC++ end-to-end or SYCL-CTS tests.
+However, the tests for a feature under active development requiring atomic
+change for tests and product can be put to
+[sycl/test/on-device](../../sycl/test/on-device) temporarily. It is developer
+responsibility to move the tests to DPC++ E2E test suite or SYCL-CTS once
+the feature is stabilized.
+
+* DPC++ end-to-end (E2E) tests which are extension to
+[LLVM\* test suite](https://github.com/intel/llvm-test-suite/tree/intel/SYCL).
+A test which requires full stack including backend runtimes (e.g. OpenCL,
+Level Zero or CUDA) should be put to DPC++ E2E test suite following
+[CONTRIBUTING](https://github.com/intel/llvm-test-suite/blob/intel/CONTRIBUTING.md).
+
+* SYCL-CTS are official 
+[Khronos\* SYCL\* conformance tests](https://github.com/KhronosGroup/SYCL-CTS).
+They verify SYCL specification compatibility. All implementation details or
+extensions are out of scope for the tests. If SYCL specification has changed
+(SYCL CTS tests conflict with recent version of SYCL specification) or change
+is required in the way the tests are built with DPC++ compiler (defined in
+[FindIntel_SYCL](https://github.com/KhronosGroup/SYCL-CTS/blob/SYCL-1.2.1/master/cmake/FindIntel_SYCL.cmake))
+pull request should be created under
+[KhronosGroup/SYCL-CTS](https://github.com/KhronosGroup/SYCL-CTS) with required
+patch.
+
+#### Run in-tree LIT tests
 
 To verify that built DPC++ toolchain is working correctly, run:
 
@@ -302,6 +335,11 @@ skipped.
 If CUDA support has been built, it is tested only if there are CUDA devices
 available.
 
+#### Run DPC++ E2E test suite
+
+Follow instructions from the link below to build and run tests:
+[README](https://github.com/intel/llvm-test-suite/tree/intel/SYCL#execution)
+
 #### Run Khronos\* SYCL\* conformance test suite (optional)
 
 Khronos\* SYCL\* conformance test suite (CTS) is intended to validate

sycl/include/CL/sycl/INTEL/esimd/detail/esimd_types.hpp

@@ -16,7 +16,6 @@
 #include <CL/sycl/detail/stl_type_traits.hpp> // to define C++14,17 extensions
 #include <CL/sycl/half_type.hpp>
 #include <cstdint>
-#include <type_traits>
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
@@ -208,8 +207,8 @@ template <typename T1, typename T2> struct computation_type {
 template <typename U> constexpr bool is_type() { return false; }
 
 template <typename U, typename T, typename... Ts> constexpr bool is_type() {
-  using UU = typename std::remove_const<U>::type;
-  using TT = typename std::remove_const<T>::type;
+  using UU = typename detail::remove_const_t<U>;
+  using TT = typename detail::remove_const_t<T>;
   return std::is_same<UU, TT>::value || is_type<UU, Ts...>();
 }
 
@@ -228,10 +227,10 @@ struct bitcast_helper {
 // Change the element type of a simd vector.
 template <typename ToEltTy, typename FromEltTy, int FromN,
           typename = csd::enable_if_t<is_vectorizable<ToEltTy>::value>>
-ESIMD_INLINE typename std::conditional<
+ESIMD_INLINE typename detail::conditional_t<
     std::is_same<FromEltTy, ToEltTy>::value, vector_type_t<FromEltTy, FromN>,
     vector_type_t<ToEltTy,
-                  bitcast_helper<ToEltTy, FromEltTy, FromN>::nToElems()>>::type
+                  bitcast_helper<ToEltTy, FromEltTy, FromN>::nToElems()>>
 bitcast(vector_type_t<FromEltTy, FromN> Val) {
   // Noop.
   if constexpr (std::is_same<FromEltTy, ToEltTy>::value)