Merge from 'sycl' to 'sycl-web' (#1)

Reapply f5360d4 as part of the conflict resolution,
as newer changes rely on it. It was previously reverted in
3a02d78.

  CONFLICT (modify/delete): clang/test/Parser/fp-floatcontrol-syntax.cpp deleted in 40287bf and modified in HEAD. Version HEAD of clang/test/Parser/fp-floatcontrol-syntax.cpp left in tree.
  CONFLICT (modify/delete): clang/test/CodeGen/fp-floatcontrol-pragma.cpp deleted in 40287bf and modified in HEAD. Version HEAD of clang/test/CodeGen/fp-floatcontrol-pragma.cpp left in tree.
  CONFLICT (content): Merge conflict in clang/lib/Sema/SemaAttr.cpp
  CONFLICT (content): Merge conflict in clang/lib/Parse/ParsePragma.cpp
  CONFLICT (content): Merge conflict in clang/include/clang/Sema/Sema.h
  CONFLICT (content): Merge conflict in clang/include/clang/Basic/LangOptions.h
  CONFLICT (content): Merge conflict in clang/include/clang/Basic/DiagnosticParseKinds.td

Author: abhinavgaba

.github/CODEOWNERS

@@ -63,6 +63,9 @@ sycl/include/CL/sycl/intel/fpga_reg.hpp @MrSidims
 sycl/include/CL/sycl/intel/pipes.hpp @MrSidims
 sycl/include/CL/sycl/pipes.hpp @MrSidims
 
+# Reduction extension
+sycl/include/CL/sycl/intel/reduction.hpp @v-klochkov
+
 # Function pointers
 sycl/include/CL/sycl/intel/function_pointer.hpp @AlexeySachkov
 sycl/source/function_pointer.cpp @AlexeySachkov
@@ -75,6 +78,7 @@ sycl/source/half_type.cpp @AlexeySachkov
 sycl/include/CL/sycl/swizzles.def @turinevgeny
 sycl/include/CL/sycl/types.hpp @turinevgeny
 
+sycl/plugins/cuda/ @intel/llvm-reviewers-cuda
 
 sycl/doc/ @pvchupin @kbobrovs
 

CONTRIBUTING.md

@@ -1,69 +1,15 @@
 # Contributing
 
 ## License
-Intel Project for LLVM\* technology is licensed under the terms of the
-Apache-2.0 with LLVM-exception license ([LICENSE.txt](llvm/LICENSE.TXT))
-to ensure our ability to contribute this project to the LLVM project
-under the same license.
 
-By contributing to this project, you agree to the Apache-2.0 with
-LLVM-exception license and copyright terms there in and release your
-contribution under these terms.
+Intel Project for LLVM\* technology is licensed under the terms of the Apache
+License v2.0 with LLVM Exceptions license ([LICENSE.txt](llvm/LICENSE.TXT)) to
+ensure our ability to contribute this project to the LLVM project under the
+same license.
 
-## Sign your work
-Please use the sign-off line at the end of your contribution. Your
-signature certifies that you wrote the contribution or otherwise have
-the right to pass it on as an open-source contribution, and that you
-agree to provide your contribution under the terms of the licenses
-noted above. The rules are pretty simple: if you can certify the
-below (from [developercertificate.org](http://developercertificate.org)):
-
-```
-Developer Certificate of Origin
-Version 1.1
-
-Copyright (C) 2004, 2006 The Linux Foundation and its contributors.
-660 York Street, Suite 102,
-San Francisco, CA 94110 USA
-
-Everyone is permitted to copy and distribute verbatim copies of this
-license document, but changing it is not allowed.
-
-Developer's Certificate of Origin 1.1
-
-By making a contribution to this project, I certify that:
-
-(a) The contribution was created in whole or in part by me and I
-    have the right to submit it under the open source license
-    indicated in the file; or
-
-(b) The contribution is based upon previous work that, to the best
-    of my knowledge, is covered under an appropriate open source
-    license and I have the right under that license to submit that
-    work with modifications, whether created in whole or in part
-    by me, under the same open source license (unless I am
-    permitted to submit under a different license), as indicated
-    in the file; or
-
-(c) The contribution was provided directly to me by some other
-    person who certified (a), (b) or (c) and I have not modified
-    it.
-
-(d) I understand and agree that this project and the contribution
-    are public and that a record of the contribution (including all
-    personal information I submit with it, including my sign-off) is
-    maintained indefinitely and may be redistributed consistent with
-    this project or the open source license(s) involved.
-```
-
-Then you just add a line to every git commit message:
-
-    Signed-off-by: Joe Smith <[email protected]>
-
-Use your real name (sorry, no pseudonyms or anonymous contributions.)
-
-If you set your `user.name` and `user.email` git configs, you can sign your
-commit automatically with `git commit -s`.
+By contributing to this project, you agree to the Apache License v2.0 with LLVM
+Exceptions and copyright terms there in and release your contribution under
+these terms.
 
 ## Contribution process
 
@@ -79,14 +25,16 @@ for more information.
     changes. See [Get Started Guide](sycl/doc/GetStartedGuide.md).
 - Prepare your patch
     - follow [LLVM coding standards](https://llvm.org/docs/CodingStandards.html)
-    - [clang-format](https://clang.llvm.org/docs/ClangFormat.html) and 
-      [clang-tidy](https://clang.llvm.org/extra/clang-tidy/) tools can be integrated into your
-      workflow to ensure formatting and stylistic compliance of your changes.
+    - [clang-format](https://clang.llvm.org/docs/ClangFormat.html) and
+      [clang-tidy](https://clang.llvm.org/extra/clang-tidy/) tools can be
+      integrated into your workflow to ensure formatting and stylistic
+      compliance of your changes.
     - use
       ```
       ./clang/tools/clang-format/git-clang-format `git merge-base origin/sycl HEAD`
       ```
-      to check the format of your current changes against the `origin/sycl` branch.
+      to check the format of your current changes against the `origin/sycl`
+      branch.
         - `-f` to also correct unstaged changes
         - `--diff` to only print the diff without applying
 - Build the project and run all tests.
@@ -125,5 +73,4 @@ Project maintainers merge pull requests using one of the following options:
 - [Create a merge commit] Used for LLVM pull-down PRs to preserve hashes of the
 commits pulled from the LLVM community repository
 
-
 *Other names and brands may be claimed as the property of others.

README.md

@@ -6,7 +6,7 @@ Intel staging area for llvm.org contribution.
 Home for Intel LLVM-based projects:
  - oneAPI Data Parallel C++ compiler - see **sycl** branch. More information on
    oneAPI and DPC++ is available at
-([https://www.oneapi.com/](https://www.oneapi.com/))
+[https://www.oneapi.com/](https://www.oneapi.com/)
    - [![Linux Post Commit Checks](https://github.com/intel/llvm/workflows/Linux%20Post%20Commit%20Checks/badge.svg)](https://github.com/intel/llvm/actions?query=workflow%3A%22Linux+Post+Commit+Checks%22)
    [![Generate Doxygen documentation](https://github.com/intel/llvm/workflows/Generate%20Doxygen%20documentation/badge.svg)](https://github.com/intel/llvm/actions?query=workflow%3A%22Generate+Doxygen+documentation%22)
 

clang/lib/Driver/ToolChains/SYCL.cpp

@@ -472,8 +472,28 @@ void SYCLToolChain::TranslateTargetOpt(const llvm::opt::ArgList &Args,
   }
 }
 
+static void addImpliedArgs(const llvm::Triple &Triple,
+                           const llvm::opt::ArgList &Args,
+                           llvm::opt::ArgStringList &CmdArgs) {
+  // Current implied args are for debug information and disabling of
+  // optimizations.
+  // TODO: Add support for other architectures (gen, x86_64) as those are
+  // being defined.
+  if (Triple.getSubArch() == llvm::Triple::NoSubArch ||
+      Triple.getSubArch() == llvm::Triple::SPIRSubArch_fpga) {
+    if (Arg *A = Args.getLastArg(options::OPT_g_Group, options::OPT__SLASH_Z7))
+      if (!A->getOption().matches(options::OPT_g0))
+        CmdArgs.push_back("-g");
+    if (Args.getLastArg(options::OPT_O0))
+      CmdArgs.push_back("-cl-opt-disable");
+  }
+}
+
 void SYCLToolChain::TranslateBackendTargetArgs(const llvm::opt::ArgList &Args,
     llvm::opt::ArgStringList &CmdArgs) const {
+  // Add any implied arguments before user defined arguments.
+  addImpliedArgs(getTriple(), Args, CmdArgs);
+
   // Handle -Xs flags.
   for (auto *A : Args) {
     // When parsing the target args, the -Xs<opt> type option applies to all

clang/lib/Sema/SPIRVBuiltins.td

@@ -485,23 +485,16 @@ foreach name = ["half_cos",
                 "half_exp", "half_exp2", "half_exp10",
                 "half_log", "half_log2", "half_log10",
                 "half_recip", "half_rsqrt",
-                "half_sin", "half_sqrt", "half_tan"] in {
-  def : ConstOCLSPVBuiltin<name, [GenTypeFloatVecAndScalar, GenTypeFloatVecAndScalar]>;
-}
-
-foreach name = ["half_divide", "half_powr"] in {
-  def : ConstOCLSPVBuiltin<name, [GenTypeFloatVecAndScalar, GenTypeFloatVecAndScalar, GenTypeFloatVecAndScalar]>;
-}
-
-foreach name = ["native_cos", "native_exp", "native_exp2", "native_exp10",
+                "half_sin", "half_sqrt", "half_tan",
+                "native_cos", "native_exp", "native_exp2", "native_exp10",
                 "native_log", "native_log2", "native_log10",
                 "native_recip", "native_rsqrt",
                 "native_sin", "native_sqrt", "native_tan"] in {
-  def : ConstOCLSPVBuiltin<name, [FGenTypeN, FGenTypeN]>;
+  def : ConstOCLSPVBuiltin<name, [GenTypeFloatVecAndScalar, GenTypeFloatVecAndScalar]>;
 }
 
-foreach name = ["native_divide", "native_powr"] in {
-  def : ConstOCLSPVBuiltin<name, [FGenTypeN, FGenTypeN, FGenTypeN]>;
+foreach name = ["half_divide", "half_powr", "native_divide", "native_powr"] in {
+  def : ConstOCLSPVBuiltin<name, [GenTypeFloatVecAndScalar, GenTypeFloatVecAndScalar, GenTypeFloatVecAndScalar]>;
 }
 
 // 2.2. Integer instructions
@@ -635,20 +628,22 @@ foreach VSize = [2, 3, 4, 8, 16] in {
       }
     }
     foreach name = ["vloada_halfn", "vload_halfn"] in {
-      def : OCLSPVBuiltin<name, [VectorType<Float, VSize>, Size, PointerType<ConstType<Half>, AS>]>;
+      def : OCLSPVBuiltin<name # "_Rfloat" # VSize, [VectorType<Float, VSize>, Size, PointerType<ConstType<Half>, AS>]>;
     }
   }
   foreach AS = [GlobalAS, LocalAS, PrivateAS, GenericAS, DefaultAS] in {
     foreach Ty = TLAll.List in {
       foreach name = ["vstoren"] in {
-        def : OCLSPVBuiltin<name, [Void, VectorType<Ty, VSize>, Size, PointerType<ConstType<Ty>, AS>]>;
+        def : OCLSPVBuiltin<name, [Void, VectorType<Ty, VSize>, Size, PointerType<Ty, AS>]>;
       }
     }
-    foreach rnd = ["", "_rte", "_rtz", "_rtp", "_rtn"] in {
-      foreach name = ["vstore_halfn" # rnd, "vstorea_halfn" # rnd] in {
-        def : OCLSPVBuiltin<name, [Void, VectorType<Float, VSize>, Size, PointerType<Half, AS>]>;
-        def : OCLSPVBuiltin<name, [Void, VectorType<Double, VSize>, Size, PointerType<Half, AS>]>;
-      }
+    foreach name = ["vstore_halfn", "vstorea_halfn"] in {
+      def : OCLSPVBuiltin<name, [Void, VectorType<Float, VSize>, Size, PointerType<Half, AS>]>;
+      def : OCLSPVBuiltin<name, [Void, VectorType<Double, VSize>, Size, PointerType<Half, AS>]>;
+    }
+    foreach name = ["vstore_halfn_r", "vstorea_halfn_r"] in {
+      def : OCLSPVBuiltin<name, [Void, VectorType<Float, VSize>, Size, PointerType<Half, AS>, UInt]>;
+      def : OCLSPVBuiltin<name, [Void, VectorType<Double, VSize>, Size, PointerType<Half, AS>, UInt]>;
     }
   }
 }
@@ -660,11 +655,13 @@ foreach AS = [GlobalAS, LocalAS, PrivateAS, ConstantAS, GenericAS, DefaultAS] in
 }
 
 foreach AS = [GlobalAS, LocalAS, PrivateAS, GenericAS, DefaultAS] in {
-  foreach rnd = ["", "_rte", "_rtz", "_rtp", "_rtn"] in {
-    foreach name = ["vstore_half" # rnd] in {
-      def : OCLSPVBuiltin<name, [Void, Float, Size, PointerType<Half, AS>]>;
-      def : OCLSPVBuiltin<name, [Void, Double, Size, PointerType<Half, AS>]>;
-    }
+  foreach name = ["vstore_half"] in {
+    def : OCLSPVBuiltin<name, [Void, Float, Size, PointerType<Half, AS>]>;
+    def : OCLSPVBuiltin<name, [Void, Double, Size, PointerType<Half, AS>]>;
+  }
+  foreach name = ["vstore_half_r"] in {
+    def : OCLSPVBuiltin<name, [Void, Float, Size, PointerType<Half, AS>, UInt]>;
+    def : OCLSPVBuiltin<name, [Void, Double, Size, PointerType<Half, AS>, UInt]>;
   }
 }
 
@@ -710,72 +707,79 @@ foreach name = ["GenericPtrMemSemantics"] in {
 }
 
 // 3.32.11. Conversion Instructions
-
-foreach IType = [UChar, UShort, UInt, ULong] in {
-  foreach FType = [Float, Double, Half] in {
-    def : SPVBuiltin<"ConvertUToF_R" # FType.Name, [FType, IType], Attr.Const>;
-    foreach rnd = ["", "_rte", "_rtz", "_rtp", "_rtn"] in {
-      def : SPVBuiltin<"ConvertFToU_R" # IType.Name # rnd, [IType, FType], Attr.Const>;
-    }
-    foreach v = [2, 3, 4, 8, 16] in {
-      def : SPVBuiltin<"ConvertFToU_R" # IType.Name # v,
-                       [VectorType<IType, v>, VectorType<FType, v>],
-                       Attr.Const>;
-      def : SPVBuiltin<"ConvertUToF_R" # FType.Name # v,
-                       [VectorType<FType, v>, VectorType<IType, v>],
-                       Attr.Const>;
-    }
-  }
-}
-
-foreach IType = [Char, Short, Int, Long] in {
-  foreach FType = [Float, Double, Half] in {
-    def : SPVBuiltin<"ConvertSToF_R" # FType.Name, [FType, IType], Attr.Const>;
-    foreach rnd = ["", "_rte", "_rtz", "_rtp", "_rtn"] in {
-      def : SPVBuiltin<"ConvertFToS_R" # IType.Name # rnd, [IType, FType], Attr.Const>;
-    }
-    foreach v = [2, 3, 4, 8, 16] in {
-      def : SPVBuiltin<"ConvertFToS_R" # IType.Name # v,
-                       [VectorType<IType, v>, VectorType<FType, v>],
-                       Attr.Const>;
-      def : SPVBuiltin<"ConvertSToF_R" # FType.Name # v,
-                       [VectorType<FType, v>, VectorType<IType, v>],
-                       Attr.Const>;
+foreach rnd = ["", "_rte", "_rtn", "_rtp", "_rtz"] in {
+  foreach IType = TLUnsignedInts.List in {
+    foreach FType = TLFloat.List in {
+      foreach sat = ["", "_sat"] in {
+        def : SPVBuiltin<"ConvertFToU_R" # IType.Name # sat # rnd, [IType, FType], Attr.Const>;
+      }
+      def : SPVBuiltin<"ConvertUToF_R" # FType.Name # rnd, [FType, IType], Attr.Const>;
+      foreach v = [2, 3, 4, 8, 16] in {
+        foreach sat = ["", "_sat"] in {
+          def : SPVBuiltin<"ConvertFToU_R" # IType.Name # v # sat # rnd,
+                           [VectorType<IType, v>, VectorType<FType, v>],
+                           Attr.Const>;
+        }
+        def : SPVBuiltin<"ConvertUToF_R" # FType.Name # v # rnd,
+                         [VectorType<FType, v>, VectorType<IType, v>],
+                         Attr.Const>;
+      }
     }
   }
-}
 
-foreach InType = TLAll.List in {
-  foreach OutType = TLUnsignedInts.List in {
-    if !ne(OutType.ElementSize, InType.ElementSize) then {
-      def : SPVBuiltin<"UConvert_R" # OutType.Name, [OutType, InType], Attr.Const>;
+  foreach IType = TLSignedInts.List in {
+    foreach FType = TLFloat.List in {
+      foreach sat = ["", "_sat"] in {
+        def : SPVBuiltin<"ConvertFToS_R" # IType.Name # sat # rnd, [IType, FType], Attr.Const>;
+      }
+      def : SPVBuiltin<"ConvertSToF_R" # FType.Name # rnd, [FType, IType], Attr.Const>;
       foreach v = [2, 3, 4, 8, 16] in {
-        def : SPVBuiltin<"UConvert_R" # OutType.Name # v,
-                         [VectorType<OutType, v>, VectorType<InType, v>],
+        foreach sat = ["", "_sat"] in {
+          def : SPVBuiltin<"ConvertFToS_R" # IType.Name # v # sat # rnd,
+                           [VectorType<IType, v>, VectorType<FType, v>],
+                           Attr.Const>;
+        }
+        def : SPVBuiltin<"ConvertSToF_R" # FType.Name # v # rnd,
+                         [VectorType<FType, v>, VectorType<IType, v>],
                          Attr.Const>;
       }
     }
   }
-  foreach OutType = TLSignedInts.List in {
-    if !ne(OutType.ElementSize, InType.ElementSize) then {
-      def : SPVBuiltin<"SConvert_R" # OutType.Name, [OutType, InType], Attr.Const>;
-      foreach v = [2, 3, 4, 8, 16] in {
-        def : SPVBuiltin<"SConvert_R" # OutType.Name # v,
-                         [VectorType<OutType, v>, VectorType<InType, v>],
-                         Attr.Const>;
+
+  foreach InType = TLFloat.List in {
+    foreach OutType = TLFloat.List in {
+      if !ne(OutType.ElementSize, InType.ElementSize) then {
+        def : SPVBuiltin<"FConvert_R" # OutType.Name # rnd, [OutType, InType], Attr.Const>;
+        foreach v = [2, 3, 4, 8, 16] in {
+          def : SPVBuiltin<"FConvert_R" # OutType.Name # v # rnd,
+                           [VectorType<OutType, v>, VectorType<InType, v>],
+                           Attr.Const>;
+        }
       }
     }
   }
 }
 
-foreach InType = TLFloat.List in {
-  foreach OutType = TLFloat.List in {
-    if !ne(OutType.ElementSize, InType.ElementSize) then {
-      def : SPVBuiltin<"FConvert_R" # OutType.Name, [OutType, InType], Attr.Const>;
-      foreach v = [2, 3, 4, 8, 16] in {
-        def : SPVBuiltin<"FConvert_R" # OutType.Name # v,
-                         [VectorType<OutType, v>, VectorType<InType, v>],
-                         Attr.Const>;
+foreach sat = ["", "_sat"] in {
+  foreach InType = TLAllInts.List in {
+    foreach OutType = TLUnsignedInts.List in {
+      if !ne(OutType.ElementSize, InType.ElementSize) then {
+        def : SPVBuiltin<"UConvert_R" # OutType.Name # sat, [OutType, InType], Attr.Const>;
+        foreach v = [2, 3, 4, 8, 16] in {
+          def : SPVBuiltin<"UConvert_R" # OutType.Name # v # sat,
+                           [VectorType<OutType, v>, VectorType<InType, v>],
+                           Attr.Const>;
+        }
+      }
+    }
+    foreach OutType = TLSignedInts.List in {
+      if !ne(OutType.ElementSize, InType.ElementSize) then {
+        def : SPVBuiltin<"SConvert_R" # OutType.Name # sat, [OutType, InType], Attr.Const>;
+        foreach v = [2, 3, 4, 8, 16] in {
+          def : SPVBuiltin<"SConvert_R" # OutType.Name # v # sat,
+                           [VectorType<OutType, v>, VectorType<InType, v>],
+                           Attr.Const>;
+        }
       }
     }
   }
@@ -809,7 +813,7 @@ foreach AS = [GlobalAS, LocalAS, PrivateAS] in {
 
 foreach Type = TLFloat.List in {
   foreach v = [2, 3, 4, 8, 16] in {
-    def : SPVBuiltin<"VectorTimesScalar", [VectorType<Type, v>, VectorType<Type, v>, Type]>;
+    def : SPVBuiltin<"VectorTimesScalar", [VectorType<Type, v>, VectorType<Type, v>, Type], Attr.Const>;
   }
 }
 
@@ -820,7 +824,6 @@ foreach name = ["Dot"] in {
 }
 
 foreach name = ["Any", "All"] in {
-  def : SPVBuiltin<name, [Bool, Bool], Attr.Const>;
   def : SPVBuiltin<name, [Bool, GenTypeSCharVecNoScalar], Attr.Const>;
 }