Skip to content

Commit e89a08a

Browse files
mcinallymcinally
committed
[SVE] MOVPRFX zero merging test renaming
Differential Revision: https://reviews.llvm.org/D80244
1 parent 08ae945 commit e89a08a

File tree

3 files changed

+122
-122
lines changed

3 files changed

+122
-122
lines changed

‎llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-merging.ll

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
; FADD
55
;
66

7-
define <vscale x 8 x half> @fadd_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
8-
; CHECK-LABEL: fadd_h:
7+
define <vscale x 8 x half> @fadd_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
8+
; CHECK-LABEL: fadd_h_zero:
99
; CHECK: movprfx z0.h, p0/z, z0.h
1010
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
1111
; CHECK-NEXT: ret
@@ -16,8 +16,8 @@ define <vscale x 8 x half> @fadd_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a
1616
ret <vscale x 8 x half> %out
1717
}
1818

19-
define <vscale x 4 x float> @fadd_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
20-
; CHECK-LABEL: fadd_s:
19+
define <vscale x 4 x float> @fadd_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
20+
; CHECK-LABEL: fadd_s_zero:
2121
; CHECK: movprfx z0.s, p0/z, z0.s
2222
; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
2323
; CHECK-NEXT: ret
@@ -28,8 +28,8 @@ define <vscale x 4 x float> @fadd_s(<vscale x 4 x i1> %pg, <vscale x 4 x float>
2828
ret <vscale x 4 x float> %out
2929
}
3030

31-
define <vscale x 2 x double> @fadd_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
32-
; CHECK-LABEL: fadd_d:
31+
define <vscale x 2 x double> @fadd_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
32+
; CHECK-LABEL: fadd_d_zero:
3333
; CHECK: movprfx z0.d, p0/z, z0.d
3434
; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d
3535
; CHECK-NEXT: ret
@@ -44,8 +44,8 @@ define <vscale x 2 x double> @fadd_d(<vscale x 2 x i1> %pg, <vscale x 2 x double
4444
; FMAX
4545
;
4646

47-
define <vscale x 8 x half> @fmax_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
48-
; CHECK-LABEL: fmax_h:
47+
define <vscale x 8 x half> @fmax_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
48+
; CHECK-LABEL: fmax_h_zero:
4949
; CHECK: movprfx z0.h, p0/z, z0.h
5050
; CHECK-NEXT: fmax z0.h, p0/m, z0.h, z1.h
5151
; CHECK-NEXT: ret
@@ -56,8 +56,8 @@ define <vscale x 8 x half> @fmax_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a
5656
ret <vscale x 8 x half> %out
5757
}
5858

59-
define <vscale x 4 x float> @fmax_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
60-
; CHECK-LABEL: fmax_s:
59+
define <vscale x 4 x float> @fmax_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
60+
; CHECK-LABEL: fmax_s_zero:
6161
; CHECK: movprfx z0.s, p0/z, z0.s
6262
; CHECK-NEXT: fmax z0.s, p0/m, z0.s, z1.s
6363
; CHECK-NEXT: ret
@@ -68,8 +68,8 @@ define <vscale x 4 x float> @fmax_s(<vscale x 4 x i1> %pg, <vscale x 4 x float>
6868
ret <vscale x 4 x float> %out
6969
}
7070

71-
define <vscale x 2 x double> @fmax_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
72-
; CHECK-LABEL: fmax_d:
71+
define <vscale x 2 x double> @fmax_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
72+
; CHECK-LABEL: fmax_d_zero:
7373
; CHECK: movprfx z0.d, p0/z, z0.d
7474
; CHECK-NEXT: fmax z0.d, p0/m, z0.d, z1.d
7575
; CHECK-NEXT: ret
@@ -84,8 +84,8 @@ define <vscale x 2 x double> @fmax_d(<vscale x 2 x i1> %pg, <vscale x 2 x double
8484
; FMAXNM
8585
;
8686

87-
define <vscale x 8 x half> @fmaxnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
88-
; CHECK-LABEL: fmaxnm_h:
87+
define <vscale x 8 x half> @fmaxnm_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
88+
; CHECK-LABEL: fmaxnm_h_zero:
8989
; CHECK: movprfx z0.h, p0/z, z0.h
9090
; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h
9191
; CHECK-NEXT: ret
@@ -96,8 +96,8 @@ define <vscale x 8 x half> @fmaxnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half>
9696
ret <vscale x 8 x half> %out
9797
}
9898

99-
define <vscale x 4 x float> @fmaxnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
100-
; CHECK-LABEL: fmaxnm_s:
99+
define <vscale x 4 x float> @fmaxnm_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
100+
; CHECK-LABEL: fmaxnm_s_zero:
101101
; CHECK: movprfx z0.s, p0/z, z0.s
102102
; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s
103103
; CHECK-NEXT: ret
@@ -108,8 +108,8 @@ define <vscale x 4 x float> @fmaxnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float
108108
ret <vscale x 4 x float> %out
109109
}
110110

111-
define <vscale x 2 x double> @fmaxnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
112-
; CHECK-LABEL: fmaxnm_d:
111+
define <vscale x 2 x double> @fmaxnm_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
112+
; CHECK-LABEL: fmaxnm_d_zero:
113113
; CHECK: movprfx z0.d, p0/z, z0.d
114114
; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d
115115
; CHECK-NEXT: ret
@@ -124,8 +124,8 @@ define <vscale x 2 x double> @fmaxnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x doub
124124
; FMIN
125125
;
126126

127-
define <vscale x 8 x half> @fmin_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
128-
; CHECK-LABEL: fmin_h:
127+
define <vscale x 8 x half> @fmin_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
128+
; CHECK-LABEL: fmin_h_zero:
129129
; CHECK: movprfx z0.h, p0/z, z0.h
130130
; CHECK-NEXT: fmin z0.h, p0/m, z0.h, z1.h
131131
; CHECK-NEXT: ret
@@ -136,8 +136,8 @@ define <vscale x 8 x half> @fmin_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a
136136
ret <vscale x 8 x half> %out
137137
}
138138

139-
define <vscale x 4 x float> @fmin_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
140-
; CHECK-LABEL: fmin_s:
139+
define <vscale x 4 x float> @fmin_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
140+
; CHECK-LABEL: fmin_s_zero:
141141
; CHECK: movprfx z0.s, p0/z, z0.s
142142
; CHECK-NEXT: fmin z0.s, p0/m, z0.s, z1.s
143143
; CHECK-NEXT: ret
@@ -148,8 +148,8 @@ define <vscale x 4 x float> @fmin_s(<vscale x 4 x i1> %pg, <vscale x 4 x float>
148148
ret <vscale x 4 x float> %out
149149
}
150150

151-
define <vscale x 2 x double> @fmin_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
152-
; CHECK-LABEL: fmin_d:
151+
define <vscale x 2 x double> @fmin_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
152+
; CHECK-LABEL: fmin_d_zero:
153153
; CHECK: movprfx z0.d, p0/z, z0.d
154154
; CHECK-NEXT: fmin z0.d, p0/m, z0.d, z1.d
155155
; CHECK-NEXT: ret
@@ -164,8 +164,8 @@ define <vscale x 2 x double> @fmin_d(<vscale x 2 x i1> %pg, <vscale x 2 x double
164164
; FMINNM
165165
;
166166

167-
define <vscale x 8 x half> @fminnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
168-
; CHECK-LABEL: fminnm_h:
167+
define <vscale x 8 x half> @fminnm_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
168+
; CHECK-LABEL: fminnm_h_zero:
169169
; CHECK: movprfx z0.h, p0/z, z0.h
170170
; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h
171171
; CHECK-NEXT: ret
@@ -176,8 +176,8 @@ define <vscale x 8 x half> @fminnm_h(<vscale x 8 x i1> %pg, <vscale x 8 x half>
176176
ret <vscale x 8 x half> %out
177177
}
178178

179-
define <vscale x 4 x float> @fminnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
180-
; CHECK-LABEL: fminnm_s:
179+
define <vscale x 4 x float> @fminnm_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
180+
; CHECK-LABEL: fminnm_s_zero:
181181
; CHECK: movprfx z0.s, p0/z, z0.s
182182
; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s
183183
; CHECK-NEXT: ret
@@ -188,8 +188,8 @@ define <vscale x 4 x float> @fminnm_s(<vscale x 4 x i1> %pg, <vscale x 4 x float
188188
ret <vscale x 4 x float> %out
189189
}
190190

191-
define <vscale x 2 x double> @fminnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
192-
; CHECK-LABEL: fminnm_d:
191+
define <vscale x 2 x double> @fminnm_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
192+
; CHECK-LABEL: fminnm_d_zero:
193193
; CHECK: movprfx z0.d, p0/z, z0.d
194194
; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d
195195
; CHECK-NEXT: ret
@@ -204,8 +204,8 @@ define <vscale x 2 x double> @fminnm_d(<vscale x 2 x i1> %pg, <vscale x 2 x doub
204204
; FMUL
205205
;
206206

207-
define <vscale x 8 x half> @fmul_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
208-
; CHECK-LABEL: fmul_h:
207+
define <vscale x 8 x half> @fmul_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
208+
; CHECK-LABEL: fmul_h_zero:
209209
; CHECK: movprfx z0.h, p0/z, z0.h
210210
; CHECK-NEXT: fmul z0.h, p0/m, z0.h, z1.h
211211
; CHECK-NEXT: ret
@@ -216,8 +216,8 @@ define <vscale x 8 x half> @fmul_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a
216216
ret <vscale x 8 x half> %out
217217
}
218218

219-
define <vscale x 4 x float> @fmul_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
220-
; CHECK-LABEL: fmul_s:
219+
define <vscale x 4 x float> @fmul_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
220+
; CHECK-LABEL: fmul_s_zero:
221221
; CHECK: movprfx z0.s, p0/z, z0.s
222222
; CHECK-NEXT: fmul z0.s, p0/m, z0.s, z1.s
223223
; CHECK-NEXT: ret
@@ -228,8 +228,8 @@ define <vscale x 4 x float> @fmul_s(<vscale x 4 x i1> %pg, <vscale x 4 x float>
228228
ret <vscale x 4 x float> %out
229229
}
230230

231-
define <vscale x 2 x double> @fmul_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
232-
; CHECK-LABEL: fmul_d:
231+
define <vscale x 2 x double> @fmul_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
232+
; CHECK-LABEL: fmul_d_zero:
233233
; CHECK: movprfx z0.d, p0/z, z0.d
234234
; CHECK-NEXT: fmul z0.d, p0/m, z0.d, z1.d
235235
; CHECK-NEXT: ret
@@ -244,8 +244,8 @@ define <vscale x 2 x double> @fmul_d(<vscale x 2 x i1> %pg, <vscale x 2 x double
244244
; FSUB
245245
;
246246

247-
define <vscale x 8 x half> @fsub_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
248-
; CHECK-LABEL: fsub_h:
247+
define <vscale x 8 x half> @fsub_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
248+
; CHECK-LABEL: fsub_h_zero:
249249
; CHECK: movprfx z0.h, p0/z, z0.h
250250
; CHECK-NEXT: fsub z0.h, p0/m, z0.h, z1.h
251251
; CHECK-NEXT: ret
@@ -256,8 +256,8 @@ define <vscale x 8 x half> @fsub_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a
256256
ret <vscale x 8 x half> %out
257257
}
258258

259-
define <vscale x 4 x float> @fsub_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
260-
; CHECK-LABEL: fsub_s:
259+
define <vscale x 4 x float> @fsub_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
260+
; CHECK-LABEL: fsub_s_zero:
261261
; CHECK: movprfx z0.s, p0/z, z0.s
262262
; CHECK-NEXT: fsub z0.s, p0/m, z0.s, z1.s
263263
; CHECK-NEXT: ret
@@ -268,8 +268,8 @@ define <vscale x 4 x float> @fsub_s(<vscale x 4 x i1> %pg, <vscale x 4 x float>
268268
ret <vscale x 4 x float> %out
269269
}
270270

271-
define <vscale x 2 x double> @fsub_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
272-
; CHECK-LABEL: fsub_d:
271+
define <vscale x 2 x double> @fsub_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
272+
; CHECK-LABEL: fsub_d_zero:
273273
; CHECK: movprfx z0.d, p0/z, z0.d
274274
; CHECK-NEXT: fsub z0.d, p0/m, z0.d, z1.d
275275
; CHECK-NEXT: ret
@@ -284,8 +284,8 @@ define <vscale x 2 x double> @fsub_d(<vscale x 2 x i1> %pg, <vscale x 2 x double
284284
; FSUBR
285285
;
286286

287-
define <vscale x 8 x half> @fsubr_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
288-
; CHECK-LABEL: fsubr_h:
287+
define <vscale x 8 x half> @fsubr_h_zero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
288+
; CHECK-LABEL: fsubr_h_zero:
289289
; CHECK: movprfx z0.h, p0/z, z0.h
290290
; CHECK-NEXT: fsubr z0.h, p0/m, z0.h, z1.h
291291
; CHECK-NEXT: ret
@@ -296,8 +296,8 @@ define <vscale x 8 x half> @fsubr_h(<vscale x 8 x i1> %pg, <vscale x 8 x half> %
296296
ret <vscale x 8 x half> %out
297297
}
298298

299-
define <vscale x 4 x float> @fsubr_s(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
300-
; CHECK-LABEL: fsubr_s:
299+
define <vscale x 4 x float> @fsubr_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
300+
; CHECK-LABEL: fsubr_s_zero:
301301
; CHECK: movprfx z0.s, p0/z, z0.s
302302
; CHECK-NEXT: fsubr z0.s, p0/m, z0.s, z1.s
303303
; CHECK-NEXT: ret
@@ -308,8 +308,8 @@ define <vscale x 4 x float> @fsubr_s(<vscale x 4 x i1> %pg, <vscale x 4 x float>
308308
ret <vscale x 4 x float> %out
309309
}
310310

311-
define <vscale x 2 x double> @fsubr_d(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
312-
; CHECK-LABEL: fsubr_d:
311+
define <vscale x 2 x double> @fsubr_d_zero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
312+
; CHECK-LABEL: fsubr_d_zero:
313313
; CHECK: movprfx z0.d, p0/z, z0.d
314314
; CHECK-NEXT: fsubr z0.d, p0/m, z0.d, z1.d
315315
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
; ADD
55
;
66

7-
define <vscale x 16 x i8> @add_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
8-
; CHECK-LABEL: add_i8:
7+
define <vscale x 16 x i8> @add_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
8+
; CHECK-LABEL: add_i8_zero:
99
; CHECK: movprfx z0.b, p0/z, z0.b
1010
; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b
1111
; CHECK-NEXT: ret
@@ -16,8 +16,8 @@ define <vscale x 16 x i8> @add_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a,
1616
ret <vscale x 16 x i8> %out
1717
}
1818

19-
define <vscale x 8 x i16> @add_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
20-
; CHECK-LABEL: add_i16:
19+
define <vscale x 8 x i16> @add_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
20+
; CHECK-LABEL: add_i16_zero:
2121
; CHECK: movprfx z0.h, p0/z, z0.h
2222
; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h
2323
; CHECK-NEXT: ret
@@ -28,8 +28,8 @@ define <vscale x 8 x i16> @add_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a,
2828
ret <vscale x 8 x i16> %out
2929
}
3030

31-
define <vscale x 4 x i32> @add_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
32-
; CHECK-LABEL: add_i32:
31+
define <vscale x 4 x i32> @add_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
32+
; CHECK-LABEL: add_i32_zero:
3333
; CHECK: movprfx z0.s, p0/z, z0.s
3434
; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
3535
; CHECK-NEXT: ret
@@ -40,8 +40,8 @@ define <vscale x 4 x i32> @add_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a,
4040
ret <vscale x 4 x i32> %out
4141
}
4242

43-
define <vscale x 2 x i64> @add_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
44-
; CHECK-LABEL: add_i64:
43+
define <vscale x 2 x i64> @add_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
44+
; CHECK-LABEL: add_i64_zero:
4545
; CHECK: movprfx z0.d, p0/z, z0.d
4646
; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d
4747
; CHECK-NEXT: ret
@@ -56,8 +56,8 @@ define <vscale x 2 x i64> @add_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a,
5656
; SUB
5757
;
5858

59-
define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
60-
; CHECK-LABEL: sub_i8:
59+
define <vscale x 16 x i8> @sub_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
60+
; CHECK-LABEL: sub_i8_zero:
6161
; CHECK: movprfx z0.b, p0/z, z0.b
6262
; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b
6363
; CHECK-NEXT: ret
@@ -68,8 +68,8 @@ define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a,
6868
ret <vscale x 16 x i8> %out
6969
}
7070

71-
define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
72-
; CHECK-LABEL: sub_i16:
71+
define <vscale x 8 x i16> @sub_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
72+
; CHECK-LABEL: sub_i16_zero:
7373
; CHECK: movprfx z0.h, p0/z, z0.h
7474
; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h
7575
; CHECK-NEXT: ret
@@ -80,8 +80,8 @@ define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a,
8080
ret <vscale x 8 x i16> %out
8181
}
8282

83-
define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
84-
; CHECK-LABEL: sub_i32:
83+
define <vscale x 4 x i32> @sub_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
84+
; CHECK-LABEL: sub_i32_zero:
8585
; CHECK: movprfx z0.s, p0/z, z0.s
8686
; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s
8787
; CHECK-NEXT: ret
@@ -92,8 +92,8 @@ define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a,
9292
ret <vscale x 4 x i32> %out
9393
}
9494

95-
define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
96-
; CHECK-LABEL: sub_i64:
95+
define <vscale x 2 x i64> @sub_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
96+
; CHECK-LABEL: sub_i64_zero:
9797
; CHECK: movprfx z0.d, p0/z, z0.d
9898
; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d
9999
; CHECK-NEXT: ret
@@ -108,8 +108,8 @@ define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a,
108108
; SUBR
109109
;
110110

111-
define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
112-
; CHECK-LABEL: subr_i8:
111+
define <vscale x 16 x i8> @subr_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
112+
; CHECK-LABEL: subr_i8_zero:
113113
; CHECK: movprfx z0.b, p0/z, z0.b
114114
; CHECK-NEXT: subr z0.b, p0/m, z0.b, z1.b
115115
; CHECK-NEXT: ret
@@ -120,8 +120,8 @@ define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a
120120
ret <vscale x 16 x i8> %out
121121
}
122122

123-
define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
124-
; CHECK-LABEL: subr_i16:
123+
define <vscale x 8 x i16> @subr_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
124+
; CHECK-LABEL: subr_i16_zero:
125125
; CHECK: movprfx z0.h, p0/z, z0.h
126126
; CHECK-NEXT: subr z0.h, p0/m, z0.h, z1.h
127127
; CHECK-NEXT: ret
@@ -132,8 +132,8 @@ define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a
132132
ret <vscale x 8 x i16> %out
133133
}
134134

135-
define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
136-
; CHECK-LABEL: subr_i32:
135+
define <vscale x 4 x i32> @subr_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
136+
; CHECK-LABEL: subr_i32_zero:
137137
; CHECK: movprfx z0.s, p0/z, z0.s
138138
; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s
139139
; CHECK-NEXT: ret
@@ -144,8 +144,8 @@ define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a
144144
ret <vscale x 4 x i32> %out
145145
}
146146

147-
define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
148-
; CHECK-LABEL: subr_i64:
147+
define <vscale x 2 x i64> @subr_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
148+
; CHECK-LABEL: subr_i64_zero:
149149
; CHECK: movprfx z0.d, p0/z, z0.d
150150
; CHECK-NEXT: subr z0.d, p0/m, z0.d, z1.d
151151
; CHECK-NEXT: ret

0 commit comments

Comments
 (0)