@@ -7373,15 +7373,34 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
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}
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return true;
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}
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+ case X86ISD::PINSRB:
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+ case X86ISD::PINSRW:
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case ISD::SCALAR_TO_VECTOR:
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case ISD::INSERT_VECTOR_ELT: {
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// Match against a insert_vector_elt/scalar_to_vector of an extract from a
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// vector, for matching src/dst vector types.
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- // TODO: Merge with PINSRB/PINSRW cases below.
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- // TODO: Handle truncate/zext/shift of scalars.
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SDValue Scl = N.getOperand(Opcode == ISD::SCALAR_TO_VECTOR ? 0 : 1);
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- SDValue SrcExtract;
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+ unsigned DstIdx = 0;
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+ if (Opcode != ISD::SCALAR_TO_VECTOR) {
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+ // Check we have an in-range constant insertion index.
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+ if (!isa<ConstantSDNode>(N.getOperand(2)) ||
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+ N.getConstantOperandAPInt(2).uge(NumElts))
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+ return false;
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+ DstIdx = N.getConstantOperandVal(2);
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+
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+ // Attempt to recognise an INSERT*(VEC, 0, DstIdx) shuffle pattern.
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+ if (X86::isZeroNode(Scl)) {
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+ Ops.push_back(N.getOperand(0));
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+ for (unsigned i = 0; i != NumElts; ++i)
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+ Mask.push_back(i == DstIdx ? SM_SentinelZero : (int)i);
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+ return true;
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+ }
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+ }
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+
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+ // Attempt to find the source vector the scalar was extracted from.
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+ // TODO: Handle truncate/zext/shift of scalars.
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+ SDValue SrcExtract;
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if ((Scl.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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Scl.getOperand(0).getValueType() == VT) ||
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(Scl.getOpcode() == X86ISD::PEXTRW &&
@@ -7390,12 +7409,8 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
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Scl.getOperand(0).getValueType() == MVT::v16i8)) {
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SrcExtract = Scl;
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}
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-
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if (!SrcExtract || !isa<ConstantSDNode>(SrcExtract.getOperand(1)))
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return false;
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- if (Opcode != ISD::SCALAR_TO_VECTOR &&
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- !isa<ConstantSDNode>(N.getOperand(2)))
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- return false;
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SDValue SrcVec = SrcExtract.getOperand(0);
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EVT SrcVT = SrcVec.getValueType();
@@ -7411,11 +7426,6 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
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if (NumSrcElts <= SrcIdx)
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return false;
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- unsigned DstIdx =
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- Opcode == ISD::SCALAR_TO_VECTOR ? 0 : N.getConstantOperandVal(2);
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- if (NumElts <= DstIdx)
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- return false;
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-
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if (Opcode == ISD::SCALAR_TO_VECTOR) {
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Ops.push_back(SrcVec);
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Mask.append(NumSrcElts, SM_SentinelUndef);
@@ -7432,44 +7442,6 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
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Mask[(Scale * DstIdx) + i + 1] = SM_SentinelZero;
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return true;
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}
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- case X86ISD::PINSRB:
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- case X86ISD::PINSRW: {
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- SDValue InVec = N.getOperand(0);
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- SDValue InScl = N.getOperand(1);
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- SDValue InIndex = N.getOperand(2);
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- if (!isa<ConstantSDNode>(InIndex) ||
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- cast<ConstantSDNode>(InIndex)->getAPIntValue().uge(NumElts))
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- return false;
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- uint64_t InIdx = N.getConstantOperandVal(2);
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-
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- // Attempt to recognise a PINSR*(VEC, 0, Idx) shuffle pattern.
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- if (X86::isZeroNode(InScl)) {
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- Ops.push_back(InVec);
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- for (unsigned i = 0; i != NumElts; ++i)
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- Mask.push_back(i == InIdx ? SM_SentinelZero : (int)i);
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- return true;
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- }
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-
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- // Attempt to recognise a PINSR*(PEXTR*) shuffle pattern.
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- // TODO: Expand this to support INSERT_VECTOR_ELT/etc.
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- unsigned ExOp =
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- (X86ISD::PINSRB == Opcode ? X86ISD::PEXTRB : X86ISD::PEXTRW);
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- if (InScl.getOpcode() != ExOp)
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- return false;
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-
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- SDValue ExVec = InScl.getOperand(0);
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- SDValue ExIndex = InScl.getOperand(1);
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- if (!isa<ConstantSDNode>(ExIndex) ||
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- cast<ConstantSDNode>(ExIndex)->getAPIntValue().uge(NumElts))
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- return false;
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- uint64_t ExIdx = InScl.getConstantOperandVal(1);
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-
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- Ops.push_back(InVec);
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- Ops.push_back(ExVec);
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- for (unsigned i = 0; i != NumElts; ++i)
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- Mask.push_back(i == InIdx ? NumElts + ExIdx : i);
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- return true;
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- }
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case X86ISD::PACKSS:
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case X86ISD::PACKUS: {
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SDValue N0 = N.getOperand(0);
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