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arsenmarsenm
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AMDGPU/GlobalISel: Fix some legalization of < dword vector stores
This avoids many instances of failing to legalize a vector truncstore of <4 x s8> to 2 bytes. We don't perfectly handle every truncstore yet, largely because the given set of legalization actions can't actually differentiate between changing the result type and changing the memory type.
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7 files changed

+1406
-234
lines changed

7 files changed

+1406
-234
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -121,10 +121,10 @@ static LegalizeMutation bitcastToRegisterType(unsigned TypeIdx) {
121121
unsigned Size = Ty.getSizeInBits();
122122

123123
LLT CoercedTy;
124-
if (Size < 32) {
124+
if (Size <= 32) {
125125
// <2 x s8> -> s16
126-
assert(Size == 16);
127-
CoercedTy = LLT::scalar(16);
126+
// <4 x s8> -> s32
127+
CoercedTy = LLT::scalar(Size);
128128
} else
129129
CoercedTy = LLT::scalarOrVector(Size / 32, 32);
130130

@@ -982,15 +982,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
982982
Actions.bitcastIf(
983983
[=](const LegalityQuery &Query) -> bool {
984984
const LLT Ty = Query.Types[0];
985+
const unsigned Size = Ty.getSizeInBits();
985986

986-
// Do not cast an extload/truncstore.
987-
if (Ty.getSizeInBits() != Query.MMODescrs[0].SizeInBits)
988-
return false;
987+
if (Size != Query.MMODescrs[0].SizeInBits)
988+
return Size <= 32 && Ty.isVector();
989989

990990
if (loadStoreBitcastWorkaround(Ty) && isRegisterType(Ty))
991991
return true;
992-
const unsigned Size = Ty.getSizeInBits();
993-
return Ty.isVector() && isRegisterSize(Size) &&
992+
return Ty.isVector() && (Size <= 32 || isRegisterSize(Size)) &&
994993
!isRegisterVectorElementType(Ty.getElementType());
995994
}, bitcastToRegisterType(0));
996995

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir

Lines changed: 168 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -4008,43 +4008,102 @@ body: |
40084008

40094009
; CI-LABEL: name: test_load_constant_v2s8_align4
40104010
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4011-
; CI: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4012-
; CI: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4013-
; CI: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4014-
; CI: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4015-
; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4011+
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4012+
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4013+
; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4014+
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4015+
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4016+
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4017+
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4018+
; CI: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4019+
; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4020+
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4021+
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
4022+
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
4023+
; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
4024+
; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
4025+
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
4026+
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
4027+
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
4028+
; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40164029
; CI: $vgpr0 = COPY [[ANYEXT]](s32)
40174030
; VI-LABEL: name: test_load_constant_v2s8_align4
40184031
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4019-
; VI: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4020-
; VI: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4021-
; VI: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4022-
; VI: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4023-
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4032+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4033+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4034+
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4035+
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4036+
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4037+
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4038+
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4039+
; VI: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4040+
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4041+
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4042+
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
4043+
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
4044+
; VI: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
4045+
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
4046+
; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
4047+
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40244048
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
40254049
; GFX9-LABEL: name: test_load_constant_v2s8_align4
40264050
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4027-
; GFX9: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4028-
; GFX9: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4029-
; GFX9: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4030-
; GFX9: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4031-
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4051+
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4052+
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4053+
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4054+
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4055+
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4056+
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4057+
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4058+
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4059+
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4060+
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4061+
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
4062+
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
4063+
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
4064+
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
4065+
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
4066+
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40324067
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
40334068
; CI-MESA-LABEL: name: test_load_constant_v2s8_align4
40344069
; CI-MESA: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4035-
; CI-MESA: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4036-
; CI-MESA: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4037-
; CI-MESA: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4038-
; CI-MESA: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4039-
; CI-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4070+
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4071+
; CI-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4072+
; CI-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4073+
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4074+
; CI-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4075+
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4076+
; CI-MESA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4077+
; CI-MESA: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4078+
; CI-MESA: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4079+
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4080+
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
4081+
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
4082+
; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
4083+
; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
4084+
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
4085+
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
4086+
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
4087+
; CI-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40404088
; CI-MESA: $vgpr0 = COPY [[ANYEXT]](s32)
40414089
; GFX9-MESA-LABEL: name: test_load_constant_v2s8_align4
40424090
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4043-
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4044-
; GFX9-MESA: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4045-
; GFX9-MESA: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4046-
; GFX9-MESA: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4047-
; GFX9-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4091+
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, align 4, addrspace 4)
4092+
; GFX9-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4093+
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4094+
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4095+
; GFX9-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4096+
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4097+
; GFX9-MESA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4098+
; GFX9-MESA: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4099+
; GFX9-MESA: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4100+
; GFX9-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4101+
; GFX9-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
4102+
; GFX9-MESA: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
4103+
; GFX9-MESA: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
4104+
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
4105+
; GFX9-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
4106+
; GFX9-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40484107
; GFX9-MESA: $vgpr0 = COPY [[ANYEXT]](s32)
40494108
%0:_(p4) = COPY $vgpr0_vgpr1
40504109
%1:_(<2 x s8>) = G_LOAD %0 :: (load 2, align 4, addrspace 4)
@@ -4061,43 +4120,102 @@ body: |
40614120

40624121
; CI-LABEL: name: test_load_constant_v2s8_align2
40634122
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4064-
; CI: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4065-
; CI: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4066-
; CI: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4067-
; CI: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4068-
; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4123+
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4124+
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4125+
; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4126+
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4127+
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4128+
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4129+
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4130+
; CI: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4131+
; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4132+
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4133+
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
4134+
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
4135+
; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
4136+
; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
4137+
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
4138+
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
4139+
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
4140+
; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40694141
; CI: $vgpr0 = COPY [[ANYEXT]](s32)
40704142
; VI-LABEL: name: test_load_constant_v2s8_align2
40714143
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4072-
; VI: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4073-
; VI: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4074-
; VI: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4075-
; VI: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4076-
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4144+
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4145+
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4146+
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4147+
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4148+
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4149+
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4150+
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4151+
; VI: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4152+
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4153+
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4154+
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
4155+
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
4156+
; VI: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
4157+
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
4158+
; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
4159+
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40774160
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
40784161
; GFX9-LABEL: name: test_load_constant_v2s8_align2
40794162
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4080-
; GFX9: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4081-
; GFX9: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4082-
; GFX9: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4083-
; GFX9: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4084-
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4163+
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4164+
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4165+
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4166+
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4167+
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4168+
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4169+
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4170+
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4171+
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4172+
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4173+
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
4174+
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
4175+
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
4176+
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
4177+
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
4178+
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40854179
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
40864180
; CI-MESA-LABEL: name: test_load_constant_v2s8_align2
40874181
; CI-MESA: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4088-
; CI-MESA: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4089-
; CI-MESA: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4090-
; CI-MESA: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4091-
; CI-MESA: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4092-
; CI-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4182+
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4183+
; CI-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4184+
; CI-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4185+
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4186+
; CI-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4187+
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4188+
; CI-MESA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4189+
; CI-MESA: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4190+
; CI-MESA: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4191+
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4192+
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
4193+
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
4194+
; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
4195+
; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
4196+
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
4197+
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
4198+
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
4199+
; CI-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
40934200
; CI-MESA: $vgpr0 = COPY [[ANYEXT]](s32)
40944201
; GFX9-MESA-LABEL: name: test_load_constant_v2s8_align2
40954202
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
4096-
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4097-
; GFX9-MESA: [[EXTRACT:%[0-9]+]]:_(<2 x s8>) = G_EXTRACT [[LOAD]](<4 x s8>), 0
4098-
; GFX9-MESA: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s8>)
4099-
; GFX9-MESA: [[MV:%[0-9]+]]:_(s16) = G_MERGE_VALUES [[UV]](s8), [[UV1]](s8)
4100-
; GFX9-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[MV]](s16)
4203+
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load 2, addrspace 4)
4204+
; GFX9-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
4205+
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
4206+
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
4207+
; GFX9-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
4208+
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
4209+
; GFX9-MESA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
4210+
; GFX9-MESA: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
4211+
; GFX9-MESA: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
4212+
; GFX9-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
4213+
; GFX9-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
4214+
; GFX9-MESA: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
4215+
; GFX9-MESA: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
4216+
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
4217+
; GFX9-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
4218+
; GFX9-MESA: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
41014219
; GFX9-MESA: $vgpr0 = COPY [[ANYEXT]](s32)
41024220
%0:_(p4) = COPY $vgpr0_vgpr1
41034221
%1:_(<2 x s8>) = G_LOAD %0 :: (load 2, align 2, addrspace 4)

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