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[AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers
This patch implements: FCVTZS: Multi-vector floating-point convert to signed integer, rounding toward zero. FCVTZU: Multi-vector floating-point convert to unsigned integer, rounding toward zero. SCVTF: Multi-vector signed integer convert to floating-point. UCVTF: Multi-vector unsigned integer convert to floating-point. for 2 and 4 registers The reference can be found here: https://developer.arm.com/documentation/ddi0602/2022-09 Depends on: D135563 Differential Revision: https://reviews.llvm.org/D135593
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‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

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@@ -362,6 +362,15 @@ defm SQCVTN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtn", 0b010>;
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defm SQCVTUN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtun", 0b110>;
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defm UQCVTN_Z4Z : sme2_int_cvt_vg4_single<"uqcvtn", 0b011>;
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def FCVTZS_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzs", 0b010>;
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def FCVTZS_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzs", 0b010>;
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def FCVTZU_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzu", 0b011>;
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def FCVTZU_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzu", 0b011>;
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def SCVTF_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"scvtf", 0b100>;
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def SCVTF_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"scvtf", 0b100>;
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def UCVTF_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"ucvtf", 0b101>;
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def UCVTF_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"ucvtf", 0b101>;
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}
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‎llvm/lib/Target/AArch64/SMEInstrFormats.td

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@@ -1794,3 +1794,33 @@ multiclass sme2_int_cvt_vg4_single<string mnemonic, bits<3> op> {
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def _StoB : sme2_cvt_vg4_single<0b0, op, ZPR8, ZZZZ_s_mul_r, mnemonic>;
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def _DtoH : sme2_cvt_vg4_single<0b1, op, ZPR16, ZZZZ_d_mul_r, mnemonic>;
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}
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class sme2_fp_cvt_vg2_multi<string mnemonic, bits<3> op>
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: I<(outs ZZ_s_mul_r:$Zd), (ins ZZ_s_mul_r:$Zn),
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mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
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bits<4> Zn;
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bits<4> Zd;
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let Inst{31-18} = 0b11000001001000;
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let Inst{17-16} = op{2-1};
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let Inst{15-10} = 0b111000;
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let Inst{9-6} = Zn;
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let Inst{5} = op{0};
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let Inst{4-1} = Zd;
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let Inst{0} = 0b0;
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}
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class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
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: I<(outs ZZZZ_s_mul_r:$Zd), (ins ZZZZ_s_mul_r:$Zn),
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mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
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bits<3> Zn;
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bits<3> Zd;
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let Inst{31-18} = 0b11000001001100;
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let Inst{17-16} = op{2-1};
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let Inst{15-10} = 0b111000;
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let Inst{9-7} = Zn;
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let Inst{6} = 0b0;
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let Inst{5} = op{0};
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let Inst{4-2} = Zd;
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let Inst{1-0} = 0b00;
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}

‎llvm/test/MC/AArch64/SME2/fcvtzs-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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fcvtzs {z0.s-z1.s}, {z0.s-z2.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzs {z0.s-z1.s}, {z0.s-z2.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzs {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: fcvtzs {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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fcvtzs {z0.d-z1.d}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzs {z0.d-z1.d}, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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‎llvm/test/MC/AArch64/SME2/fcvtzs.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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fcvtzs {z0.s, z1.s}, {z0.s, z1.s} // 11000001-00100001-11100000-00000000
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// CHECK-INST: fcvtzs { z0.s, z1.s }, { z0.s, z1.s }
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// CHECK-ENCODING: [0x00,0xe0,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e000 <unknown>
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fcvtzs {z20.s, z21.s}, {z10.s, z11.s} // 11000001-00100001-11100001-01010100
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// CHECK-INST: fcvtzs { z20.s, z21.s }, { z10.s, z11.s }
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// CHECK-ENCODING: [0x54,0xe1,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e154 <unknown>
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fcvtzs {z22.s, z23.s}, {z12.s, z13.s} // 11000001-00100001-11100001-10010110
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// CHECK-INST: fcvtzs { z22.s, z23.s }, { z12.s, z13.s }
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// CHECK-ENCODING: [0x96,0xe1,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e196 <unknown>
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fcvtzs {z30.s, z31.s}, {z30.s, z31.s} // 11000001-00100001-11100011-11011110
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// CHECK-INST: fcvtzs { z30.s, z31.s }, { z30.s, z31.s }
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// CHECK-ENCODING: [0xde,0xe3,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e3de <unknown>
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fcvtzs {z0.s - z3.s}, {z0.s - z3.s} // 11000001-00110001-11100000-00000000
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// CHECK-INST: fcvtzs { z0.s - z3.s }, { z0.s - z3.s }
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// CHECK-ENCODING: [0x00,0xe0,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e000 <unknown>
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fcvtzs {z20.s - z23.s}, {z8.s - z11.s} // 11000001-00110001-11100001-00010100
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// CHECK-INST: fcvtzs { z20.s - z23.s }, { z8.s - z11.s }
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// CHECK-ENCODING: [0x14,0xe1,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e114 <unknown>
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fcvtzs {z20.s - z23.s}, {z12.s - z15.s} // 11000001-00110001-11100001-10010100
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// CHECK-INST: fcvtzs { z20.s - z23.s }, { z12.s - z15.s }
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// CHECK-ENCODING: [0x94,0xe1,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e194 <unknown>
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fcvtzs {z28.s - z31.s}, {z28.s - z31.s} // 11000001-00110001-11100011-10011100
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// CHECK-INST: fcvtzs { z28.s - z31.s }, { z28.s - z31.s }
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// CHECK-ENCODING: [0x9c,0xe3,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e39c <unknown>
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‎llvm/test/MC/AArch64/SME2/fcvtzu-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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fcvtzu {z0.s-z1.s}, {z0.s-z2.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzu {z0.s-z1.s}, {z0.s-z2.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzu {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: fcvtzu {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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fcvtzu {z0.d-z1.d}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvtzu {z0.d-z1.d}, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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‎llvm/test/MC/AArch64/SME2/fcvtzu.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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fcvtzu {z0.s, z1.s}, {z0.s, z1.s} // 11000001-00100001-11100000-00100000
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// CHECK-INST: fcvtzu { z0.s, z1.s }, { z0.s, z1.s }
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// CHECK-ENCODING: [0x20,0xe0,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e020 <unknown>
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fcvtzu {z20.s, z21.s}, {z10.s, z11.s} // 11000001-00100001-11100001-01110100
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// CHECK-INST: fcvtzu { z20.s, z21.s }, { z10.s, z11.s }
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// CHECK-ENCODING: [0x74,0xe1,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e174 <unknown>
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fcvtzu {z22.s, z23.s}, {z12.s, z13.s} // 11000001-00100001-11100001-10110110
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// CHECK-INST: fcvtzu { z22.s, z23.s }, { z12.s, z13.s }
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// CHECK-ENCODING: [0xb6,0xe1,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e1b6 <unknown>
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fcvtzu {z30.s, z31.s}, {z30.s, z31.s} // 11000001-00100001-11100011-11111110
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// CHECK-INST: fcvtzu { z30.s, z31.s }, { z30.s, z31.s }
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// CHECK-ENCODING: [0xfe,0xe3,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c121e3fe <unknown>
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fcvtzu {z0.s - z3.s}, {z0.s - z3.s} // 11000001-00110001-11100000-00100000
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// CHECK-INST: fcvtzu { z0.s - z3.s }, { z0.s - z3.s }
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// CHECK-ENCODING: [0x20,0xe0,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e020 <unknown>
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fcvtzu {z20.s - z23.s}, {z8.s - z11.s} // 11000001-00110001-11100001-00110100
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// CHECK-INST: fcvtzu { z20.s - z23.s }, { z8.s - z11.s }
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// CHECK-ENCODING: [0x34,0xe1,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e134 <unknown>
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fcvtzu {z20.s - z23.s}, {z12.s - z15.s} // 11000001-00110001-11100001-10110100
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// CHECK-INST: fcvtzu { z20.s - z23.s }, { z12.s - z15.s }
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// CHECK-ENCODING: [0xb4,0xe1,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e1b4 <unknown>
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fcvtzu {z28.s - z31.s}, {z28.s - z31.s} // 11000001-00110001-11100011-10111100
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// CHECK-INST: fcvtzu { z28.s - z31.s }, { z28.s - z31.s }
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// CHECK-ENCODING: [0xbc,0xe3,0x31,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c131e3bc <unknown>
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‎llvm/test/MC/AArch64/SME2/scvtf-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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scvtf {z0.s-z3.s}, {z0.s-z4.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: scvtf {z0.s-z3.s}, {z0.s-z4.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: scvtf {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf {z0.s-z3.s}, {z1.s-z5.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.s-z5.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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scvtf {z0.s-z3.s}, {z1.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.h-z3.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SME2/scvtf.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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scvtf {z0.s, z1.s}, {z0.s, z1.s} // 11000001-00100010-11100000-00000000
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// CHECK-INST: scvtf { z0.s, z1.s }, { z0.s, z1.s }
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// CHECK-ENCODING: [0x00,0xe0,0x22,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c122e000 <unknown>
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scvtf {z20.s, z21.s}, {z10.s, z11.s} // 11000001-00100010-11100001-01010100
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// CHECK-INST: scvtf { z20.s, z21.s }, { z10.s, z11.s }
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// CHECK-ENCODING: [0x54,0xe1,0x22,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c122e154 <unknown>
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scvtf {z22.s, z23.s}, {z12.s, z13.s} // 11000001-00100010-11100001-10010110
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// CHECK-INST: scvtf { z22.s, z23.s }, { z12.s, z13.s }
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// CHECK-ENCODING: [0x96,0xe1,0x22,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c122e196 <unknown>
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scvtf {z30.s, z31.s}, {z30.s, z31.s} // 11000001-00100010-11100011-11011110
34+
// CHECK-INST: scvtf { z30.s, z31.s }, { z30.s, z31.s }
35+
// CHECK-ENCODING: [0xde,0xe3,0x22,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c122e3de <unknown>
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scvtf {z0.s - z3.s}, {z0.s - z3.s} // 11000001-00110010-11100000-00000000
41+
// CHECK-INST: scvtf { z0.s - z3.s }, { z0.s - z3.s }
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// CHECK-ENCODING: [0x00,0xe0,0x32,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c132e000 <unknown>
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scvtf {z20.s - z23.s}, {z8.s - z11.s} // 11000001-00110010-11100001-00010100
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// CHECK-INST: scvtf { z20.s - z23.s }, { z8.s - z11.s }
48+
// CHECK-ENCODING: [0x14,0xe1,0x32,0xc1]
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// CHECK-ERROR: instruction requires: sme2
50+
// CHECK-UNKNOWN: c132e114 <unknown>
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scvtf {z20.s - z23.s}, {z12.s - z15.s} // 11000001-00110010-11100001-10010100
53+
// CHECK-INST: scvtf { z20.s - z23.s }, { z12.s - z15.s }
54+
// CHECK-ENCODING: [0x94,0xe1,0x32,0xc1]
55+
// CHECK-ERROR: instruction requires: sme2
56+
// CHECK-UNKNOWN: c132e194 <unknown>
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scvtf {z28.s - z31.s}, {z28.s - z31.s} // 11000001-00110010-11100011-10011100
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// CHECK-INST: scvtf { z28.s - z31.s }, { z28.s - z31.s }
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// CHECK-ENCODING: [0x9c,0xe3,0x32,0xc1]
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// CHECK-ERROR: instruction requires: sme2
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// CHECK-UNKNOWN: c132e39c <unknown>
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‎llvm/test/MC/AArch64/SME2/ucvtf-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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ucvtf {z0.s-z3.s}, {z0.s-z4.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: ucvtf {z0.s-z3.s}, {z0.s-z4.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtf {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: ucvtf {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ucvtf {z0.s-z3.s}, {z1.s-z5.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: ucvtf {z0.s-z3.s}, {z1.s-z5.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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ucvtf {z0.s-z3.s}, {z1.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ucvtf {z0.s-z3.s}, {z1.h-z3.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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