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[ARM] Fix tail predication predicate tracking
Clear the CurrentPredicate when we find an instruction which would completely overwrite the VPR. This fix essentially means we're back to not really being able to handle VPT instructions when tail predicating. Differential Revision: https://reviews.llvm.org/D87610
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6 files changed

+107
-33
lines changed

6 files changed

+107
-33
lines changed

‎llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -874,6 +874,7 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
874874
if (MI->getOpcode() != ARM::MVE_VPST) {
875875
assert(MI->findRegisterDefOperandIdx(ARM::VPR) != -1 &&
876876
"VPT does not implicitly define VPR?!");
877+
CurrentPredicate.clear();
877878
CurrentPredicate.insert(MI);
878879
}
879880

@@ -913,6 +914,16 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
913914
}
914915
}
915916

917+
// If this instruction defines the VPR, update the predicate for the
918+
// proceeding instructions.
919+
if (IsDef) {
920+
// Clear the existing predicate when we're not in VPT Active state.
921+
if (!isVectorPredicated(MI))
922+
CurrentPredicate.clear();
923+
CurrentPredicate.insert(MI);
924+
LLVM_DEBUG(dbgs() << "ARM Loops: Adding Predicate: " << *MI);
925+
}
926+
916927
// If we find a vpr def that is not already predicated on the vctp, we've
917928
// got disjoint predicates that may not be equivalent when we do the
918929
// conversion.
@@ -928,9 +939,9 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
928939
// If we find an instruction that has been marked as not valid for tail
929940
// predication, only allow the instruction if it's contained within a valid
930941
// VPT block.
931-
if ((Flags & ARMII::ValidForTailPredication) == 0 && !IsUse) {
942+
if ((Flags & ARMII::ValidForTailPredication) == 0) {
932943
LLVM_DEBUG(dbgs() << "ARM Loops: Can't tail predicate: " << *MI);
933-
return false;
944+
return IsUse;
934945
}
935946

936947
// If the instruction is already explicitly predicated, then the conversion

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -464,19 +464,28 @@ define dso_local arm_aapcs_vfpcc void @range_test(i32* noalias nocapture %arg, i
464464
; CHECK-NEXT: it eq
465465
; CHECK-NEXT: popeq {r7, pc}
466466
; CHECK-NEXT: .LBB5_1: @ %bb4
467+
; CHECK-NEXT: add.w r12, r3, #3
468+
; CHECK-NEXT: mov.w lr, #1
469+
; CHECK-NEXT: bic r12, r12, #3
470+
; CHECK-NEXT: sub.w r12, r12, #4
471+
; CHECK-NEXT: add.w lr, lr, r12, lsr #2
467472
; CHECK-NEXT: mov.w r12, #0
468-
; CHECK-NEXT: dlstp.32 lr, r3
473+
; CHECK-NEXT: dls lr, lr
469474
; CHECK-NEXT: .LBB5_2: @ %bb12
470475
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
471-
; CHECK-NEXT: vldrw.u32 q0, [r0]
472-
; CHECK-NEXT: vptt.i32 ne, q0, zr
476+
; CHECK-NEXT: vctp.32 r3
477+
; CHECK-NEXT: vpst
478+
; CHECK-NEXT: vldrwt.u32 q0, [r0]
479+
; CHECK-NEXT: vpttt.i32 ne, q0, zr
473480
; CHECK-NEXT: vcmpt.s32 le, q0, r2
481+
; CHECK-NEXT: vctpt.32 r3
474482
; CHECK-NEXT: vldrwt.u32 q1, [r1], #16
475483
; CHECK-NEXT: add.w r12, r12, #4
484+
; CHECK-NEXT: subs r3, #4
476485
; CHECK-NEXT: vmul.i32 q0, q1, q0
477486
; CHECK-NEXT: vpst
478487
; CHECK-NEXT: vstrwt.32 q0, [r0], #16
479-
; CHECK-NEXT: letp lr, .LBB5_2
488+
; CHECK-NEXT: le lr, .LBB5_2
480489
; CHECK-NEXT: @ %bb.3: @ %bb32
481490
; CHECK-NEXT: pop {r7, pc}
482491
bb:

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -135,27 +135,34 @@ body: |
135135
; CHECK: successors: %bb.2(0x80000000)
136136
; CHECK: liveins: $r0, $r1, $r2, $r3
137137
; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg
138+
; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
138139
; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg
140+
; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg
139141
; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 2 from %ir.mask.gep9)
142+
; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
143+
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
140144
; CHECK: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg
145+
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
141146
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
142147
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
143148
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
144149
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
145-
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
150+
; CHECK: $lr = t2DLS killed renamable $lr
146151
; CHECK: bb.2.bb9:
147152
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
148-
; CHECK: liveins: $lr, $q0, $r0, $r1, $r3, $r12
153+
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
149154
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
150-
; CHECK: MVE_VPST 4, implicit $vpr
155+
; CHECK: MVE_VPST 2, implicit $vpr
156+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
151157
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
152158
; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
159+
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
153160
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
154161
; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8)
155162
; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
156163
; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
157164
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
158-
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
165+
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
159166
; CHECK: bb.3.bb27:
160167
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
161168
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,13 +7,23 @@ define void @remat_vctp(i32* %arg, i32* %arg1, i32* %arg2, i32* %arg3, i32* %arg
77
; CHECK-NEXT: push {r4, r5, r7, lr}
88
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
99
; CHECK-NEXT: ldrd r5, r12, [sp, #80]
10+
; CHECK-NEXT: cmp.w r12, #4
11+
; CHECK-NEXT: mov r4, r12
1012
; CHECK-NEXT: vmvn.i32 q0, #0x80000000
13+
; CHECK-NEXT: it ge
14+
; CHECK-NEXT: movge r4, #4
1115
; CHECK-NEXT: vmov.i32 q1, #0x3f
16+
; CHECK-NEXT: sub.w r4, r12, r4
1217
; CHECK-NEXT: vmov.i32 q2, #0x1
13-
; CHECK-NEXT: dlstp.32 lr, r12
18+
; CHECK-NEXT: add.w lr, r4, #3
19+
; CHECK-NEXT: movs r4, #1
20+
; CHECK-NEXT: add.w lr, r4, lr, lsr #2
21+
; CHECK-NEXT: dls lr, lr
1422
; CHECK-NEXT: .LBB0_1: @ %bb6
1523
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
16-
; CHECK-NEXT: vldrw.u32 q4, [r1], #16
24+
; CHECK-NEXT: vctp.32 r12
25+
; CHECK-NEXT: vpst
26+
; CHECK-NEXT: vldrwt.u32 q4, [r1], #16
1727
; CHECK-NEXT: vabs.s32 q5, q4
1828
; CHECK-NEXT: vcls.s32 q3, q5
1929
; CHECK-NEXT: vshl.u32 q5, q5, q3
@@ -31,13 +41,15 @@ define void @remat_vctp(i32* %arg, i32* %arg1, i32* %arg2, i32* %arg3, i32* %arg
3141
; CHECK-NEXT: vqshl.s32 q5, q5, #1
3242
; CHECK-NEXT: vpt.s32 lt, q4, zr
3343
; CHECK-NEXT: vnegt.s32 q5, q5
44+
; CHECK-NEXT: vctp.32 r12
45+
; CHECK-NEXT: sub.w r12, r12, #4
3446
; CHECK-NEXT: vpst
3547
; CHECK-NEXT: vldrwt.u32 q4, [r0], #16
3648
; CHECK-NEXT: vqrdmulh.s32 q4, q4, q5
3749
; CHECK-NEXT: vpstt
3850
; CHECK-NEXT: vstrwt.32 q4, [r2], #16
3951
; CHECK-NEXT: vstrwt.32 q3, [r3], #16
40-
; CHECK-NEXT: letp lr, .LBB0_1
52+
; CHECK-NEXT: le lr, .LBB0_1
4153
; CHECK-NEXT: @ %bb.2: @ %bb44
4254
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
4355
; CHECK-NEXT: pop {r4, r5, r7, pc}

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -118,24 +118,32 @@ body: |
118118
; CHECK: bb.1.bb3:
119119
; CHECK: successors: %bb.2(0x80000000)
120120
; CHECK: liveins: $r0, $r1, $r2, $r3
121+
; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
122+
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
123+
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
121124
; CHECK: $vpr = VMSR_P0 killed $r3, 14 /* CC::al */, $noreg
125+
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
122126
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
123127
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
124-
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
128+
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
129+
; CHECK: $lr = t2DLS killed renamable $lr
125130
; CHECK: bb.2.bb9:
126131
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
127-
; CHECK: liveins: $lr, $r0, $r1, $r3
132+
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
128133
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
129-
; CHECK: MVE_VPST 8, implicit $vpr
130-
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
134+
; CHECK: MVE_VPST 4, implicit $vpr
135+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
136+
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
137+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
138+
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
131139
; CHECK: MVE_VPST 4, implicit $vpr
132140
; CHECK: renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr
133141
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
134142
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
135143
; CHECK: MVE_VPST 8, implicit $vpr
136144
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
137145
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
138-
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
146+
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
139147
; CHECK: bb.3.bb27:
140148
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
141149
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir

Lines changed: 42 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -215,17 +215,26 @@ body: |
215215
; CHECK: bb.1.vector.ph:
216216
; CHECK: successors: %bb.2(0x80000000)
217217
; CHECK: liveins: $r0, $r1, $r2
218+
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
218219
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
220+
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
221+
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
222+
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
223+
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
219224
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
220-
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
225+
; CHECK: $lr = t2DLS killed renamable $lr
221226
; CHECK: bb.2.vector.body:
222227
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
223-
; CHECK: liveins: $lr, $q0, $r0, $r2, $r3
224-
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg
225-
; CHECK: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr
228+
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
229+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
230+
; CHECK: MVE_VPST 8, implicit $vpr
231+
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr
232+
; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
226233
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr
234+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr
227235
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr
228-
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
236+
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
237+
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
229238
; CHECK: bb.3.for.cond.cleanup:
230239
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
231240
bb.0.entry:
@@ -593,17 +602,26 @@ body: |
593602
; CHECK: bb.1.vector.ph:
594603
; CHECK: successors: %bb.2(0x80000000)
595604
; CHECK: liveins: $r0, $r1, $r2
605+
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
596606
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
607+
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
608+
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
609+
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
610+
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
597611
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
598-
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
612+
; CHECK: $lr = t2DLS killed renamable $lr
599613
; CHECK: bb.2.vector.body:
600614
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
601-
; CHECK: liveins: $lr, $q0, $r0, $r2, $r3
602-
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg
603-
; CHECK: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr
615+
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
616+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
617+
; CHECK: MVE_VPST 8, implicit $vpr
618+
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr
619+
; CHECK: MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr
604620
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr
621+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr
605622
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr
606-
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
623+
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
624+
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
607625
; CHECK: bb.3.for.cond.cleanup:
608626
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
609627
;
@@ -713,17 +731,26 @@ body: |
713731
; CHECK: bb.1.vector.ph:
714732
; CHECK: successors: %bb.2(0x80000000)
715733
; CHECK: liveins: $r0, $r1, $r2
734+
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
716735
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
736+
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
737+
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
738+
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
739+
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
717740
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
718-
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
741+
; CHECK: $lr = t2DLS killed renamable $lr
719742
; CHECK: bb.2.vector.body:
720743
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
721-
; CHECK: liveins: $lr, $q0, $r0, $r2, $r3
722-
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg
723-
; CHECK: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr
744+
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
745+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
746+
; CHECK: MVE_VPST 8, implicit $vpr
747+
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr
748+
; CHECK: MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr
724749
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr
750+
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr
725751
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr
726-
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
752+
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
753+
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
727754
; CHECK: bb.3.for.cond.cleanup:
728755
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
729756
bb.0.entry:

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