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davemgreendavemgreen
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[VectorCombine] Add Cmp and Select for shuffleToIdentity
Other than some additional checks needed for compare predicates and selects with scalar condition operands, these are relatively simple additions to what already exists. I will rebase over llvm#92766, but already had the patch for this version.
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2 files changed

+22
-28
lines changed

2 files changed

+22
-28
lines changed

‎llvm/lib/Transforms/Vectorize/VectorCombine.cpp

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1757,6 +1757,13 @@ bool VectorCombine::foldShuffleToIdentity(Instruction &I) {
17571757
return false;
17581758
if (IL.first->getValueID() != Item[0].first->getValueID())
17591759
return false;
1760+
if (auto *CI = dyn_cast<CmpInst>(IL.first))
1761+
if (CI->getPredicate() !=
1762+
cast<CmpInst>(Item[0].first)->getPredicate())
1763+
return false;
1764+
if (auto *SI = dyn_cast<SelectInst>(IL.first))
1765+
if (!isa<VectorType>(SI->getOperand(0)->getType()))
1766+
return false;
17601767
if (isa<CallInst>(IL.first) && !isa<IntrinsicInst>(IL.first))
17611768
return false;
17621769
auto *II = dyn_cast<IntrinsicInst>(IL.first);
@@ -1769,12 +1776,17 @@ bool VectorCombine::foldShuffleToIdentity(Instruction &I) {
17691776

17701777
// Check the operator is one that we support. We exclude div/rem in case
17711778
// they hit UB from poison lanes.
1772-
if (isa<BinaryOperator>(Item[0].first) &&
1773-
!cast<BinaryOperator>(Item[0].first)->isIntDivRem()) {
1779+
if ((isa<BinaryOperator>(Item[0].first) &&
1780+
!cast<BinaryOperator>(Item[0].first)->isIntDivRem()) ||
1781+
isa<CmpInst>(Item[0].first)) {
17741782
Worklist.push_back(GenerateInstLaneVectorFromOperand(Item, 0));
17751783
Worklist.push_back(GenerateInstLaneVectorFromOperand(Item, 1));
17761784
} else if (isa<UnaryOperator>(Item[0].first)) {
17771785
Worklist.push_back(GenerateInstLaneVectorFromOperand(Item, 0));
1786+
} else if (isa<SelectInst>(Item[0].first)) {
1787+
Worklist.push_back(GenerateInstLaneVectorFromOperand(Item, 0));
1788+
Worklist.push_back(GenerateInstLaneVectorFromOperand(Item, 1));
1789+
Worklist.push_back(GenerateInstLaneVectorFromOperand(Item, 2));
17781790
} else if (auto *II = dyn_cast<IntrinsicInst>(Item[0].first);
17791791
II && isTriviallyVectorizable(II->getIntrinsicID())) {
17801792
for (unsigned Op = 0, E = II->getNumOperands() - 1; Op < E; Op++) {
@@ -1834,6 +1846,10 @@ bool VectorCombine::foldShuffleToIdentity(Instruction &I) {
18341846
if (auto BI = dyn_cast<BinaryOperator>(I))
18351847
return Builder.CreateBinOp((Instruction::BinaryOps)BI->getOpcode(),
18361848
Ops[0], Ops[1]);
1849+
if (auto CI = dyn_cast<CmpInst>(I))
1850+
return Builder.CreateCmp(CI->getPredicate(), Ops[0], Ops[1]);
1851+
if (auto SI = dyn_cast<SelectInst>(I))
1852+
return Builder.CreateSelect(Ops[0], Ops[1], Ops[2], "", SI);
18371853
if (II)
18381854
return Builder.CreateIntrinsic(DstTy, II->getIntrinsicID(), Ops);
18391855
assert(isa<UnaryInstruction>(I) &&

‎llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll

Lines changed: 4 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -399,19 +399,8 @@ define <8 x i8> @extrause_shuffle(<8 x i8> %a, <8 x i8> %b) {
399399

400400
define <8 x i8> @icmpsel(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
401401
; CHECK-LABEL: @icmpsel(
402-
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x i8> [[A:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
403-
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
404-
; CHECK-NEXT: [[BB:%.*]] = shufflevector <8 x i8> [[B:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
405-
; CHECK-NEXT: [[BT:%.*]] = shufflevector <8 x i8> [[B]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
406-
; CHECK-NEXT: [[CB:%.*]] = shufflevector <8 x i8> [[C:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
407-
; CHECK-NEXT: [[CT:%.*]] = shufflevector <8 x i8> [[C]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
408-
; CHECK-NEXT: [[DB:%.*]] = shufflevector <8 x i8> [[D:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
409-
; CHECK-NEXT: [[DT:%.*]] = shufflevector <8 x i8> [[D]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
410-
; CHECK-NEXT: [[ABT1:%.*]] = icmp slt <4 x i8> [[AT]], [[BT]]
411-
; CHECK-NEXT: [[ABB1:%.*]] = icmp slt <4 x i8> [[AB]], [[BB]]
412-
; CHECK-NEXT: [[ABT:%.*]] = select <4 x i1> [[ABT1]], <4 x i8> [[CT]], <4 x i8> [[DT]]
413-
; CHECK-NEXT: [[ABB:%.*]] = select <4 x i1> [[ABB1]], <4 x i8> [[CB]], <4 x i8> [[DB]]
414-
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[ABT]], <4 x i8> [[ABB]], <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
402+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <8 x i8> [[A:%.*]], [[B:%.*]]
403+
; CHECK-NEXT: [[R:%.*]] = select <8 x i1> [[TMP1]], <8 x i8> [[C:%.*]], <8 x i8> [[D:%.*]]
415404
; CHECK-NEXT: ret <8 x i8> [[R]]
416405
;
417406
%ab = shufflevector <8 x i8> %a, <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -465,19 +454,8 @@ define <8 x i8> @icmpsel_diffentcond(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x
465454

466455
define <8 x i8> @fcmpsel(<8 x half> %a, <8 x half> %b, <8 x i8> %c, <8 x i8> %d) {
467456
; CHECK-LABEL: @fcmpsel(
468-
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x half> [[A:%.*]], <8 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
469-
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x half> [[A]], <8 x half> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
470-
; CHECK-NEXT: [[BB:%.*]] = shufflevector <8 x half> [[B:%.*]], <8 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
471-
; CHECK-NEXT: [[BT:%.*]] = shufflevector <8 x half> [[B]], <8 x half> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
472-
; CHECK-NEXT: [[CB:%.*]] = shufflevector <8 x i8> [[C:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
473-
; CHECK-NEXT: [[CT:%.*]] = shufflevector <8 x i8> [[C]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
474-
; CHECK-NEXT: [[DB:%.*]] = shufflevector <8 x i8> [[D:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
475-
; CHECK-NEXT: [[DT:%.*]] = shufflevector <8 x i8> [[D]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
476-
; CHECK-NEXT: [[ABT1:%.*]] = fcmp olt <4 x half> [[AT]], [[BT]]
477-
; CHECK-NEXT: [[ABB1:%.*]] = fcmp olt <4 x half> [[AB]], [[BB]]
478-
; CHECK-NEXT: [[ABT:%.*]] = select <4 x i1> [[ABT1]], <4 x i8> [[CT]], <4 x i8> [[DT]]
479-
; CHECK-NEXT: [[ABB:%.*]] = select <4 x i1> [[ABB1]], <4 x i8> [[CB]], <4 x i8> [[DB]]
480-
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[ABT]], <4 x i8> [[ABB]], <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
457+
; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt <8 x half> [[A:%.*]], [[B:%.*]]
458+
; CHECK-NEXT: [[R:%.*]] = select <8 x i1> [[TMP1]], <8 x i8> [[C:%.*]], <8 x i8> [[D:%.*]]
481459
; CHECK-NEXT: ret <8 x i8> [[R]]
482460
;
483461
%ab = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>

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