How is interrupts handled in multi-core?

[drakejest]

Im assigning core 2 to handle data acquisition to the sensors, these involves multiple interrupts and i was wonderinng how the arduino pico core handles these. ( I dont see an interrupt section in the docs)

If i do an attachInterrupt() on loop2/setup2 i assume it will only interrupt core 2 right? Core 1 will remain unaffected?

Does that also mean noInterrupts() and Interrupts() will only apply to the specific core they are called upon?

[earlephilhower]

It's core0 and core1, not core1 and core2, so be sure to use setup1() and loop1() not setup2(). :)

Multicore you should read the RP2040 datasheet and be aware that Arduino functions/libraries are generally not multicore or multithread safe.

At a high level, each core has its own controller so only the core you enable GPIO interrupts on will take the IRQ. Only attachInterrupt on one core or you'll have some very odd behavior. Same for calling things like LittleFS/etc. Serial is special-cased and can be called from both cores and things generally "just work" but that's the exception, not the rule.

noInterrupts etc. only affect the core it is run on since there are separate interrupt controllers. Look at the rp2040.idleOtherCore docs if you need to freeze the other core. Also look at the PicoSDK mutexes if you need to synchronize things between cores.

It's not really that hard, but it does take care to use both cores successfully. General multicore/multithread rules apply here.

[earlephilhower]

There is only one GPIO block and only 1 interrupt for all pins, not individual IRQs for each pin. So you end up with a race condition because depending on which core services the IRQ first. Or, worse, you get both taking the interrupt at the same time and trying to write to a single GPIO control register at the same time.

[drakejest]

so there is only 1 IRQ for both cores? If you are only reading data from GPIO there should be no problem with race condition as you are not writing to any register. Its more of if pin 5 triggers the interrupt core0 should stop what its doing and process the data, core1 continue as normal. if pin 3 triggers the interrupt core0 continue as normal, core1 should stop and process the data.

[earlephilhower]

You need to clear the IRQ when you're done or it'll never re-trigger, so that's the crux of the issue. And who/when it's cleared is the problem.

It's really not going to work well, but feel free to give it a try. You might be able to hack the core to make something like that happen, but I would recommend thinking of another way to get what you want done. Service all IRQs from one block on one core and then, maybe, generate a different IRQ (i.e. the intercore FIFO) to do something elsewhere if needed.

[drakejest]

Speaking of race conditions and only one GPIO register, wont there be a problem just by doing digitalWrite() on both cores?

[drakejest]

You need to clear the IRQ when you're done or it'll never re-trigger, so that's the crux of the issue. And who/when it's cleared is the problem.

Ahh this clears things up, this is the part that i did not know needs to be done. So yes there is no way around it, has to be done on one core only.