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Reland "[NVPTX] Add support for atomic add for f16 type" (llvm#85197)
atom.add.noftz.f16 is supported since SM 7.0
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‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6100,6 +6100,9 @@ NVPTXTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
61006100

61016101
if (AI->isFloatingPointOperation()) {
61026102
if (AI->getOperation() == AtomicRMWInst::BinOp::FAdd) {
6103+
if (Ty->isHalfTy() && STI.getSmVersion() >= 70 &&
6104+
STI.getPTXVersion() >= 63)
6105+
return AtomicExpansionKind::None;
61036106
if (Ty->isFloatTy())
61046107
return AtomicExpansionKind::None;
61056108
if (Ty->isDoubleTy() && STI.hasAtomAddF64())

‎llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1520,7 +1520,7 @@ multiclass F_ATOMIC_2_imp<ValueType ptrT, NVPTXRegClass ptrclass,
15201520
def imm : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, IMMType:$b),
15211521
!strconcat("atom", SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b;", ""),
15221522
[(set (regT regclass:$dst), (IntOp (ptrT ptrclass:$addr), IMM:$b))]>,
1523-
Requires<Pred>;
1523+
Requires<!if(!eq(TypeStr, ".f16"), [Predicate<"false">], Pred)>;
15241524
}
15251525
multiclass F_ATOMIC_2<ValueType regT, NVPTXRegClass regclass, string SpaceStr, string TypeStr,
15261526
string OpcStr, PatFrag IntOp, Operand IMMType, SDNode IMM,
@@ -1630,6 +1630,13 @@ defm INT_PTX_ATOM_ADD_GEN_64 : F_ATOMIC_2<i64, Int64Regs, "", ".u64", ".add",
16301630
defm INT_PTX_ATOM_ADD_GEN_64_USE_G : F_ATOMIC_2<i64, Int64Regs, ".global", ".u64",
16311631
".add", atomic_load_add_64_gen, i64imm, imm>;
16321632

1633+
defm INT_PTX_ATOM_ADD_G_F16 : F_ATOMIC_2<f16, Int16Regs, ".global", ".f16", ".add.noftz",
1634+
atomic_load_add_g, f16imm, fpimm, [hasSM<70>, hasPTX<63>]>;
1635+
defm INT_PTX_ATOM_ADD_S_F16 : F_ATOMIC_2<f16, Int16Regs, ".shared", ".f16", ".add.noftz",
1636+
atomic_load_add_s, f16imm, fpimm, [hasSM<70>, hasPTX<63>]>;
1637+
defm INT_PTX_ATOM_ADD_GEN_F16 : F_ATOMIC_2<f16, Int16Regs, "", ".f16", ".add.noftz",
1638+
atomic_load_add_gen, f16imm, fpimm, [hasSM<70>, hasPTX<63>]>;
1639+
16331640
defm INT_PTX_ATOM_ADD_G_F32 : F_ATOMIC_2<f32, Float32Regs, ".global", ".f32", ".add",
16341641
atomic_load_add_g, f32imm, fpimm>;
16351642
defm INT_PTX_ATOM_ADD_S_F32 : F_ATOMIC_2<f32, Float32Regs, ".shared", ".f32", ".add",
@@ -2007,6 +2014,9 @@ multiclass ATOM2P_impl<string AsmStr, Intrinsic Intr,
20072014
SDNode Imm, ValueType ImmTy,
20082015
list<Predicate> Preds> {
20092016
let AddedComplexity = 1 in {
2017+
def : ATOM23_impl<AsmStr, regT, regclass, Preds,
2018+
(ins Int16Regs:$src, regclass:$b),
2019+
(Intr (i16 Int16Regs:$src), (regT regclass:$b))>;
20102020
def : ATOM23_impl<AsmStr, regT, regclass, Preds,
20112021
(ins Int32Regs:$src, regclass:$b),
20122022
(Intr (i32 Int32Regs:$src), (regT regclass:$b))>;
@@ -2017,6 +2027,9 @@ multiclass ATOM2P_impl<string AsmStr, Intrinsic Intr,
20172027
// tablegen can't infer argument types from Intrinsic (though it can
20182028
// from Instruction) so we have to enforce specific type on
20192029
// immediates via explicit cast to ImmTy.
2030+
def : ATOM23_impl<AsmStr, regT, regclass, Preds,
2031+
(ins Int16Regs:$src, ImmType:$b),
2032+
(Intr (i16 Int16Regs:$src), (ImmTy Imm:$b))>;
20202033
def : ATOM23_impl<AsmStr, regT, regclass, Preds,
20212034
(ins Int32Regs:$src, ImmType:$b),
20222035
(Intr (i32 Int32Regs:$src), (ImmTy Imm:$b))>;
@@ -2136,6 +2149,8 @@ multiclass ATOM2_add_impl<string OpStr> {
21362149
defm _s32 : ATOM2S_impl<OpStr, "i", "s32", i32, Int32Regs, i32imm, imm, i32, []>;
21372150
defm _u32 : ATOM2S_impl<OpStr, "i", "u32", i32, Int32Regs, i32imm, imm, i32, []>;
21382151
defm _u64 : ATOM2S_impl<OpStr, "i", "u64", i64, Int64Regs, i64imm, imm, i64, []>;
2152+
defm _f16 : ATOM2S_impl<OpStr, "f", "f16", f16, Int16Regs, f16imm, fpimm, f16,
2153+
[hasSM<70>, hasPTX<63>]>;
21392154
defm _f32 : ATOM2S_impl<OpStr, "f", "f32", f32, Float32Regs, f32imm, fpimm, f32,
21402155
[]>;
21412156
defm _f64 : ATOM2S_impl<OpStr, "f", "f64", f64, Float64Regs, f64imm, fpimm, f64,

‎llvm/test/CodeGen/NVPTX/atomics-sm70.ll

Lines changed: 142 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,142 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc < %s -march=nvptx -mcpu=sm_70 -mattr=+ptx63 | FileCheck %s --check-prefixes=CHECK
3+
; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | FileCheck %s --check-prefixes=CHECK64
4+
; RUN: llc < %s -march=nvptx -mcpu=sm_70 -mattr=+ptx62 | FileCheck %s --check-prefixes=CHECKPTX62
5+
; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_70 -mattr=+ptx63 | %ptxas-verify -arch=sm_70 %}
6+
; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | %ptxas-verify -arch=sm_70 %}
7+
; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -march=nvptx -mcpu=sm_70 -mattr=+ptx62 | %ptxas-verify -arch=sm_70 %}
8+
9+
target triple = "nvptx64-nvidia-cuda"
10+
11+
define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, half %val) {
12+
; CHECK-LABEL: test(
13+
; CHECK: {
14+
; CHECK-NEXT: .reg .b16 %rs<7>;
15+
; CHECK-NEXT: .reg .b32 %r<4>;
16+
; CHECK-EMPTY:
17+
; CHECK-NEXT: // %bb.0:
18+
; CHECK-NEXT: ld.param.u32 %r1, [test_param_0];
19+
; CHECK-NEXT: ld.param.b16 %rs1, [test_param_3];
20+
; CHECK-NEXT: atom.add.noftz.f16 %rs2, [%r1], %rs1;
21+
; CHECK-NEXT: ld.param.u32 %r2, [test_param_1];
22+
; CHECK-NEXT: mov.b16 %rs3, 0x3C00;
23+
; CHECK-NEXT: atom.add.noftz.f16 %rs4, [%r1], %rs3;
24+
; CHECK-NEXT: ld.param.u32 %r3, [test_param_2];
25+
; CHECK-NEXT: atom.global.add.noftz.f16 %rs5, [%r2], %rs1;
26+
; CHECK-NEXT: atom.shared.add.noftz.f16 %rs6, [%r3], %rs1;
27+
; CHECK-NEXT: ret;
28+
;
29+
; CHECK64-LABEL: test(
30+
; CHECK64: {
31+
; CHECK64-NEXT: .reg .b16 %rs<7>;
32+
; CHECK64-NEXT: .reg .b64 %rd<4>;
33+
; CHECK64-EMPTY:
34+
; CHECK64-NEXT: // %bb.0:
35+
; CHECK64-NEXT: ld.param.u64 %rd1, [test_param_0];
36+
; CHECK64-NEXT: ld.param.b16 %rs1, [test_param_3];
37+
; CHECK64-NEXT: atom.add.noftz.f16 %rs2, [%rd1], %rs1;
38+
; CHECK64-NEXT: ld.param.u64 %rd2, [test_param_1];
39+
; CHECK64-NEXT: mov.b16 %rs3, 0x3C00;
40+
; CHECK64-NEXT: atom.add.noftz.f16 %rs4, [%rd1], %rs3;
41+
; CHECK64-NEXT: ld.param.u64 %rd3, [test_param_2];
42+
; CHECK64-NEXT: atom.global.add.noftz.f16 %rs5, [%rd2], %rs1;
43+
; CHECK64-NEXT: atom.shared.add.noftz.f16 %rs6, [%rd3], %rs1;
44+
; CHECK64-NEXT: ret;
45+
;
46+
; CHECKPTX62-LABEL: test(
47+
; CHECKPTX62: {
48+
; CHECKPTX62-NEXT: .reg .pred %p<5>;
49+
; CHECKPTX62-NEXT: .reg .b16 %rs<19>;
50+
; CHECKPTX62-NEXT: .reg .b32 %r<58>;
51+
; CHECKPTX62-EMPTY:
52+
; CHECKPTX62-NEXT: // %bb.0:
53+
; CHECKPTX62-NEXT: ld.param.b16 %rs1, [test_param_3];
54+
; CHECKPTX62-NEXT: ld.param.u32 %r23, [test_param_2];
55+
; CHECKPTX62-NEXT: ld.param.u32 %r22, [test_param_1];
56+
; CHECKPTX62-NEXT: ld.param.u32 %r24, [test_param_0];
57+
; CHECKPTX62-NEXT: and.b32 %r1, %r24, -4;
58+
; CHECKPTX62-NEXT: and.b32 %r25, %r24, 3;
59+
; CHECKPTX62-NEXT: shl.b32 %r2, %r25, 3;
60+
; CHECKPTX62-NEXT: mov.b32 %r26, 65535;
61+
; CHECKPTX62-NEXT: shl.b32 %r27, %r26, %r2;
62+
; CHECKPTX62-NEXT: not.b32 %r3, %r27;
63+
; CHECKPTX62-NEXT: ld.u32 %r54, [%r1];
64+
; CHECKPTX62-NEXT: $L__BB0_1: // %atomicrmw.start
65+
; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1
66+
; CHECKPTX62-NEXT: shr.u32 %r28, %r54, %r2;
67+
; CHECKPTX62-NEXT: cvt.u16.u32 %rs2, %r28;
68+
; CHECKPTX62-NEXT: add.rn.f16 %rs4, %rs2, %rs1;
69+
; CHECKPTX62-NEXT: cvt.u32.u16 %r29, %rs4;
70+
; CHECKPTX62-NEXT: shl.b32 %r30, %r29, %r2;
71+
; CHECKPTX62-NEXT: and.b32 %r31, %r54, %r3;
72+
; CHECKPTX62-NEXT: or.b32 %r32, %r31, %r30;
73+
; CHECKPTX62-NEXT: atom.cas.b32 %r6, [%r1], %r54, %r32;
74+
; CHECKPTX62-NEXT: setp.ne.s32 %p1, %r6, %r54;
75+
; CHECKPTX62-NEXT: mov.u32 %r54, %r6;
76+
; CHECKPTX62-NEXT: @%p1 bra $L__BB0_1;
77+
; CHECKPTX62-NEXT: // %bb.2: // %atomicrmw.end
78+
; CHECKPTX62-NEXT: ld.u32 %r55, [%r1];
79+
; CHECKPTX62-NEXT: $L__BB0_3: // %atomicrmw.start9
80+
; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1
81+
; CHECKPTX62-NEXT: shr.u32 %r33, %r55, %r2;
82+
; CHECKPTX62-NEXT: cvt.u16.u32 %rs6, %r33;
83+
; CHECKPTX62-NEXT: mov.b16 %rs8, 0x3C00;
84+
; CHECKPTX62-NEXT: add.rn.f16 %rs9, %rs6, %rs8;
85+
; CHECKPTX62-NEXT: cvt.u32.u16 %r34, %rs9;
86+
; CHECKPTX62-NEXT: shl.b32 %r35, %r34, %r2;
87+
; CHECKPTX62-NEXT: and.b32 %r36, %r55, %r3;
88+
; CHECKPTX62-NEXT: or.b32 %r37, %r36, %r35;
89+
; CHECKPTX62-NEXT: atom.cas.b32 %r9, [%r1], %r55, %r37;
90+
; CHECKPTX62-NEXT: setp.ne.s32 %p2, %r9, %r55;
91+
; CHECKPTX62-NEXT: mov.u32 %r55, %r9;
92+
; CHECKPTX62-NEXT: @%p2 bra $L__BB0_3;
93+
; CHECKPTX62-NEXT: // %bb.4: // %atomicrmw.end8
94+
; CHECKPTX62-NEXT: and.b32 %r10, %r22, -4;
95+
; CHECKPTX62-NEXT: shl.b32 %r38, %r22, 3;
96+
; CHECKPTX62-NEXT: and.b32 %r11, %r38, 24;
97+
; CHECKPTX62-NEXT: shl.b32 %r40, %r26, %r11;
98+
; CHECKPTX62-NEXT: not.b32 %r12, %r40;
99+
; CHECKPTX62-NEXT: ld.global.u32 %r56, [%r10];
100+
; CHECKPTX62-NEXT: $L__BB0_5: // %atomicrmw.start27
101+
; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1
102+
; CHECKPTX62-NEXT: shr.u32 %r41, %r56, %r11;
103+
; CHECKPTX62-NEXT: cvt.u16.u32 %rs11, %r41;
104+
; CHECKPTX62-NEXT: add.rn.f16 %rs13, %rs11, %rs1;
105+
; CHECKPTX62-NEXT: cvt.u32.u16 %r42, %rs13;
106+
; CHECKPTX62-NEXT: shl.b32 %r43, %r42, %r11;
107+
; CHECKPTX62-NEXT: and.b32 %r44, %r56, %r12;
108+
; CHECKPTX62-NEXT: or.b32 %r45, %r44, %r43;
109+
; CHECKPTX62-NEXT: atom.global.cas.b32 %r15, [%r10], %r56, %r45;
110+
; CHECKPTX62-NEXT: setp.ne.s32 %p3, %r15, %r56;
111+
; CHECKPTX62-NEXT: mov.u32 %r56, %r15;
112+
; CHECKPTX62-NEXT: @%p3 bra $L__BB0_5;
113+
; CHECKPTX62-NEXT: // %bb.6: // %atomicrmw.end26
114+
; CHECKPTX62-NEXT: and.b32 %r16, %r23, -4;
115+
; CHECKPTX62-NEXT: shl.b32 %r46, %r23, 3;
116+
; CHECKPTX62-NEXT: and.b32 %r17, %r46, 24;
117+
; CHECKPTX62-NEXT: shl.b32 %r48, %r26, %r17;
118+
; CHECKPTX62-NEXT: not.b32 %r18, %r48;
119+
; CHECKPTX62-NEXT: ld.shared.u32 %r57, [%r16];
120+
; CHECKPTX62-NEXT: $L__BB0_7: // %atomicrmw.start45
121+
; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1
122+
; CHECKPTX62-NEXT: shr.u32 %r49, %r57, %r17;
123+
; CHECKPTX62-NEXT: cvt.u16.u32 %rs15, %r49;
124+
; CHECKPTX62-NEXT: add.rn.f16 %rs17, %rs15, %rs1;
125+
; CHECKPTX62-NEXT: cvt.u32.u16 %r50, %rs17;
126+
; CHECKPTX62-NEXT: shl.b32 %r51, %r50, %r17;
127+
; CHECKPTX62-NEXT: and.b32 %r52, %r57, %r18;
128+
; CHECKPTX62-NEXT: or.b32 %r53, %r52, %r51;
129+
; CHECKPTX62-NEXT: atom.shared.cas.b32 %r21, [%r16], %r57, %r53;
130+
; CHECKPTX62-NEXT: setp.ne.s32 %p4, %r21, %r57;
131+
; CHECKPTX62-NEXT: mov.u32 %r57, %r21;
132+
; CHECKPTX62-NEXT: @%p4 bra $L__BB0_7;
133+
; CHECKPTX62-NEXT: // %bb.8: // %atomicrmw.end44
134+
; CHECKPTX62-NEXT: ret;
135+
%r1 = atomicrmw fadd ptr %dp0, half %val seq_cst
136+
%r2 = atomicrmw fadd ptr %dp0, half 1.0 seq_cst
137+
%r3 = atomicrmw fadd ptr addrspace(1) %dp1, half %val seq_cst
138+
%r4 = atomicrmw fadd ptr addrspace(3) %dp3, half %val seq_cst
139+
ret void
140+
}
141+
142+
attributes #1 = { argmemonly nounwind }

‎llvm/test/CodeGen/NVPTX/atomics.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,13 @@ define float @atomicrmw_add_f32_generic(ptr %addr, float %val) {
175175
ret float %ret
176176
}
177177

178+
; CHECK-LABEL: atomicrmw_add_f16_generic
179+
define half @atomicrmw_add_f16_generic(ptr %addr, half %val) {
180+
; CHECK: atom.cas
181+
%ret = atomicrmw fadd ptr %addr, half %val seq_cst
182+
ret half %ret
183+
}
184+
178185
; CHECK-LABEL: atomicrmw_add_f32_addrspace1
179186
define float @atomicrmw_add_f32_addrspace1(ptr addrspace(1) %addr, float %val) {
180187
; CHECK: atom.global.add.f32

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