Merge pull request #49 from esp-rs/xtensa-rt-alloc-fixes

xtensa-lx changes, alloc fixes and clean up

Author: MabezDev

.vscode/settings.json

@@ -0,0 +1,3 @@
+{
+    "rust-analyzer.cargo.target": "x86_64-unknown-linux-gnu"
+}

Cargo.toml

@@ -32,19 +32,19 @@ alloc = ["linked_list_allocator"]
 mem = []
 
 # Enable the `rt` feature of the `esp32` crate.
-rt = ["esp32/rt", "xtensa-lx6-rt"]
+rt = ["esp32/rt", "xtensa-lx-rt"]
 
 
 [dependencies]
-esp32-hal-proc-macros = { version = "=0.1.0", path = "procmacros" }
+esp32-hal-proc-macros = { version = "=0.2.0", path = "procmacros" }
 
-xtensa-lx6-rt = { version = "0.4.0", optional = true }
-xtensa-lx6 = "0.2.0"
-esp32 = { version = "0.7.0", default-features = false }
+xtensa-lx-rt = { version = "0.5.0", optional = true, features = ["lx6"] }
+xtensa-lx = { version = "0.3.0", features = ["lx6"]}
+esp32 = "0.10.0"
 bare-metal = "0.2"
 nb = "0.1.2"
 embedded-hal = { version = "0.2.3", features = ["unproven"] }
-linked_list_allocator = { version = "=0.8.4", optional = true, default-features = false, features = ["alloc_ref"] }
+linked_list_allocator = { version = "0.8.5", optional = true, default-features = false, features = ["alloc_ref"] }
 void = { version = "1.0.2", default-features = false }
 
 [dev-dependencies]

examples/blinky.rs

@@ -1,21 +1,19 @@
 #![no_std]
 #![no_main]
 
-extern crate esp32_hal as hal;
-extern crate panic_halt;
-extern crate xtensa_lx6_rt;
-
 use esp32_hal::target;
 use hal::prelude::*;
-use xtensa_lx6::timer::get_cycle_count;
+use xtensa_lx::timer::get_cycle_count;
+use panic_halt as _;
+use esp32_hal as hal;
 
 /// The default clock source is the onboard crystal
 /// In most cases 40mhz (but can be as low as 2mhz depending on the board)
 const CORE_HZ: u32 = 40_000_000;
 
 const WDT_WKEY_VALUE: u32 = 0x50D83AA1;
 
-#[no_mangle]
+#[entry]
 fn main() -> ! {
     let dp = target::Peripherals::take().expect("Failed to obtain Peripherals");
 

examples/exception.rs

@@ -19,8 +19,8 @@ use esp32_hal::Core::PRO;
 // !!! Cannot use CriticalSectionSpinLockMutex here, because an NMI is fires from within a locked
 // section which leads to a deadlock in the NMI interrupt handler. This is not a problem in this
 // case as this is a single threaded example. !!!
-static TX: xtensa_lx6::mutex::CriticalSectionMutex<Option<esp32_hal::serial::Tx<esp32::UART0>>> =
-    xtensa_lx6::mutex::CriticalSectionMutex::new(None);
+static TX: xtensa_lx::mutex::CriticalSectionMutex<Option<esp32_hal::serial::Tx<esp32::UART0>>> =
+    xtensa_lx::mutex::CriticalSectionMutex::new(None);
 
 fn locked_print(str: &str) {
     (&TX).lock(|tx| {
@@ -30,7 +30,7 @@ fn locked_print(str: &str) {
             tx,
             "    {}, Level: {}",
             str,
-            xtensa_lx6::interrupt::get_level()
+            xtensa_lx::interrupt::get_level()
         )
         .unwrap();
     });
@@ -78,8 +78,8 @@ fn random_name() {
 #[exception]
 #[ram]
 fn other_exception(
-    cause: xtensa_lx6_rt::exception::ExceptionCause,
-    frame: xtensa_lx6_rt::exception::Context,
+    cause: xtensa_lx_rt::exception::ExceptionCause,
+    frame: xtensa_lx_rt::exception::Context,
 ) {
     (&TX).lock(|tx| {
         let tx = tx.as_mut().unwrap();

examples/gpio.rs

@@ -122,7 +122,7 @@ fn handle_gpio_interrupt() {
             writeln!(
                 serial,
                 "  Interrupt level: {}, pin state: {}",
-                xtensa_lx6::interrupt::get_level(),
+                xtensa_lx::interrupt::get_level(),
                 gpio.is_high().unwrap()
             )
             .unwrap();

examples/mem.rs

@@ -17,7 +17,7 @@ use esp32_hal::mem::{memcmp, memcpy, memcpy_reverse, memset};
 use esp32_hal::serial::{config::Config, Serial};
 use esp32_hal::target;
 
-use xtensa_lx6::timer::get_cycle_count;
+use xtensa_lx::timer::get_cycle_count;
 
 #[macro_use]
 extern crate alloc;

examples/multicore.rs

@@ -12,7 +12,7 @@ use esp32_hal::dprintln;
 use esp32_hal::serial::{config::Config, Serial};
 use esp32_hal::target;
 
-use xtensa_lx6::{get_stack_pointer, timer::get_cycle_count};
+use xtensa_lx::{get_stack_pointer, timer::get_cycle_count};
 
 const BLINK_HZ: Hertz = Hertz(1);
 

examples/ram.rs

@@ -12,7 +12,7 @@ use esp32_hal::dprintln;
 use esp32_hal::serial::{config::Config, Serial};
 use esp32_hal::target;
 
-use xtensa_lx6::get_program_counter;
+use xtensa_lx::get_program_counter;
 
 #[entry]
 fn main() -> ! {

examples/rtccntl.rs

@@ -128,7 +128,7 @@ fn main() -> ! {
 
                 x = x.wrapping_add(1);
 
-                let ccount = xtensa_lx6::timer::get_cycle_count();
+                let ccount = xtensa_lx::timer::get_cycle_count();
                 let ccount_diff = ccount.wrapping_sub(prev_ccount);
 
                 writeln!(

examples/timer.rs

@@ -161,7 +161,7 @@ fn main() -> ! {
                 timer0.get_value(),
                 timer1.get_value(),
                 timer2.get_value(),
-                xtensa_lx6::timer::get_cycle_count()
+                xtensa_lx::timer::get_cycle_count()
             )
             .unwrap();
             if let Ok(_) = timer1.wait() {

procmacros/Cargo.toml

@@ -7,7 +7,7 @@ keywords = ["esp32", "esp32-hal", "runtime", "startup"]
 license = "MIT OR Apache-2.0"
 name = "esp32-hal-proc-macros"
 repository = "https://github.com/esp-rs/xtensa-lx6-rt"
-version = "0.1.0"
+version = "0.2.0"
 edition = "2018"
 
 [lib]

src/alloc.rs

@@ -149,26 +149,17 @@ unsafe impl GlobalAlloc for Allocator {
 }
 
 extern crate alloc;
-use alloc::alloc::{AllocErr, AllocInit, AllocRef, MemoryBlock};
+use alloc::alloc::{AllocErr, AllocRef};
 
 unsafe impl AllocRef for Allocator {
-    fn alloc(&mut self, layout: Layout, init: AllocInit) -> Result<MemoryBlock, AllocErr> {
+    fn alloc(&mut self, layout: Layout) -> Result<NonNull<[u8]>, AllocErr> {
         if layout.size() == 0 {
-            return Ok(MemoryBlock {
-                ptr: layout.dangling(),
-                size: 0,
-            });
+            return Ok(NonNull::slice_from_raw_parts(layout.dangling(), 0));
         }
         let ptr = unsafe { GlobalAlloc::alloc(self, layout) };
-        if ptr != 0 as *mut u8 {
-            let block = MemoryBlock {
-                ptr: NonNull::new(ptr).ok_or(AllocErr)?,
-                size: layout.size(),
-            };
-            unsafe { init.init(block) };
-            Ok(block)
-        } else {
-            Err(AllocErr)
+        match NonNull::new(ptr) {
+            Some(ptr) => Ok(NonNull::slice_from_raw_parts(ptr, layout.size())),
+            None => Err(AllocErr)
         }
     }
     unsafe fn dealloc(&mut self, ptr: NonNull<u8>, layout: Layout) {

src/clock_control/cpu.rs

@@ -4,7 +4,7 @@
 use super::Error;
 use crate::target;
 use crate::Core::{self, APP, PRO};
-use xtensa_lx6::set_stack_pointer;
+use xtensa_lx::set_stack_pointer;
 
 static mut START_CORE1_FUNCTION: Option<fn() -> !> = None;
 
@@ -119,12 +119,12 @@ impl super::ClockControl {
         }
 
         // disables interrupts
-        xtensa_lx6::interrupt::set_mask(0);
+        xtensa_lx::interrupt::set_mask(0);
 
         // reset cycle compare registers
-        xtensa_lx6::timer::set_ccompare0(0);
-        xtensa_lx6::timer::set_ccompare1(0);
-        xtensa_lx6::timer::set_ccompare2(0);
+        xtensa_lx::timer::set_ccompare0(0);
+        xtensa_lx::timer::set_ccompare1(0);
+        xtensa_lx::timer::set_ccompare2(0);
 
         // set stack pointer to end of memory: no need to retain stack up to this point
         set_stack_pointer(&mut _stack_end_cpu1);
@@ -136,7 +136,7 @@ impl super::ClockControl {
     ///
     /// The second core will start running with the function `entry`.
     pub fn start_app_core(&mut self, entry: fn() -> !) -> Result<(), Error> {
-        if !xtensa_lx6::is_debugger_attached()
+        if !xtensa_lx::is_debugger_attached()
             && self
                 .dport_control
                 .appcpu_ctrl_b()

src/clock_control/mod.rs

@@ -23,7 +23,7 @@ use crate::target::rtccntl::clk_conf::*;
 use crate::target::rtccntl::cntl::*;
 use crate::target::{APB_CTRL, RTCCNTL, TIMG0};
 use core::fmt;
-use xtensa_lx6::timer::{delay, get_cycle_count};
+use xtensa_lx::timer::{delay, get_cycle_count};
 
 pub mod config;
 pub mod cpu;

src/dport.rs

@@ -4,8 +4,8 @@
 //! Registers needed in other blocks can be split off.
 //!
 use crate::target::{dport, DPORT};
-use xtensa_lx6::mutex::mutex_trait::Mutex;
-use xtensa_lx6::mutex::CriticalSectionSpinLockMutex;
+use xtensa_lx::mutex::mutex_trait::Mutex;
+use xtensa_lx::mutex::CriticalSectionSpinLockMutex;
 
 /// Cpu Period Configuration Register
 pub struct ClockControl {}

src/external_ram.rs

@@ -38,7 +38,7 @@ pub(super) unsafe fn init() {
     if &_external_heap_start as *const u32 > (&_external_ram_start as *const u32).add(get_size()) {
         panic!("External RAM too small for data");
     }
-    xtensa_lx6_rt::zero_bss(&mut _external_bss_start, &mut _external_bss_end);
+    xtensa_lx_rt::zero_bss(&mut _external_bss_start, &mut _external_bss_end);
 }
 
 /// Calculate the size of external RAM by reading and writing at defined intervals while

src/interrupt.rs

@@ -4,15 +4,15 @@
 //! This module redirects the cpu interrupts handler to registered peripheral interrupt handlers.
 //!
 //! Interrupt handlers are defined using the [Interrupt](attr.interrupt.html) attribute.
-//! (Note that this is a distinct attribute from the one in the [xtensa_lx6_rt](xtensa_lx6_rt)
+//! (Note that this is a distinct attribute from the one in the [xtensa_lx_rt](xtensa_lx_rt)
 //! crate.)
 //!
 //! To enable the interrupt and assign to a specific interrupt level use
 //! the [enable] or [enable_with_priority] functions. (This is in addition to enabling the
 //! interrupt in the respective peripherals.)
 //!
 //! To have lowest latency possible you can use the
-//! [Interrupt](../../xtensa_lx6_rt/attr.interrupt.html) attribute from the xtensa_lx6_rt crate
+//! [Interrupt](../../xtensa_lx_rt/attr.interrupt.html) attribute from the xtensa_lx_rt crate
 //! to define low level/naked interrupt handlers. (This will override the interrupt
 //! handling offered by this crate for that specific interrupt level. This should especially be
 //! considered when using Level 7 = Non Maskable Interrupt level as these will not be turned off
@@ -38,7 +38,7 @@ pub use crate::target::{
 use crate::Core::{self, APP, PRO};
 use bare_metal::Nr;
 pub use proc_macros::interrupt;
-pub use xtensa_lx6::interrupt::{self, free};
+pub use xtensa_lx::interrupt::{self, free};
 
 /// Interrupt errors
 #[derive(Debug)]
@@ -213,43 +213,43 @@ static mut INTERRUPT_LEVELS: [u128; 8] = [0u128; 8];
 static INTERRUPT_LEVELS_MUTEX: CriticalSectionSpinLockMutex<bool> =
     CriticalSectionSpinLockMutex::new(false);
 
-#[xtensa_lx6_rt::interrupt(1)]
+#[xtensa_lx_rt::interrupt(1)]
 #[ram]
 unsafe fn level_1_handler(level: u32) {
     handle_interrupts(level)
 }
 
-#[xtensa_lx6_rt::interrupt(2)]
+#[xtensa_lx_rt::interrupt(2)]
 #[ram]
 unsafe fn level_2_handler(level: u32) {
     handle_interrupts(level)
 }
 
-#[xtensa_lx6_rt::interrupt(3)]
+#[xtensa_lx_rt::interrupt(3)]
 #[ram]
 unsafe fn level_3_handler(level: u32) {
     handle_interrupts(level)
 }
 
-#[xtensa_lx6_rt::interrupt(4)]
+#[xtensa_lx_rt::interrupt(4)]
 #[ram]
 unsafe fn level_4_handler(level: u32) {
     handle_interrupts(level)
 }
 
-#[xtensa_lx6_rt::interrupt(5)]
+#[xtensa_lx_rt::interrupt(5)]
 #[ram]
 unsafe fn level_5_handler(level: u32) {
     handle_interrupts(level)
 }
 
-#[xtensa_lx6_rt::interrupt(6)]
+#[xtensa_lx_rt::interrupt(6)]
 #[ram]
 unsafe fn level_6_handler(level: u32) {
     handle_interrupts(level)
 }
 
-#[xtensa_lx6_rt::interrupt(7)]
+#[xtensa_lx_rt::interrupt(7)]
 #[ram]
 unsafe fn level_7_handler(level: u32) {
     handle_interrupts(level)

src/lib.rs

@@ -18,6 +18,7 @@
 #![feature(const_fn)]
 #![cfg_attr(feature = "alloc", feature(allocator_api))]
 #![cfg_attr(feature = "alloc", feature(alloc_layout_extra))]
+#![cfg_attr(feature = "alloc", feature(nonnull_slice_from_raw_parts))]
 
 pub use embedded_hal as hal;
 pub use esp32 as target;
@@ -76,17 +77,17 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
     // initialization to zero needs to be done by the application
 
     // Initialize RTC RAM
-    xtensa_lx6_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
-    xtensa_lx6_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end);
+    xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
+    xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end);
 
     #[cfg(feature = "external_ram")]
     external_ram::init();
 
     // set stack pointer to end of memory: no need to retain stack up to this point
-    xtensa_lx6::set_stack_pointer(&mut _stack_end_cpu0);
+    xtensa_lx::set_stack_pointer(&mut _stack_end_cpu0);
 
     // continue with default reset handler
-    xtensa_lx6_rt::Reset();
+    xtensa_lx_rt::Reset();
 }
 
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
@@ -96,7 +97,7 @@ pub enum Core {
 }
 
 pub fn get_core() -> Core {
-    match ((xtensa_lx6::get_processor_id() >> 13) & 1) != 0 {
+    match ((xtensa_lx::get_processor_id() >> 13) & 1) != 0 {
         false => Core::PRO,
         true => Core::APP,
     }

src/prelude.rs

@@ -7,7 +7,7 @@
 //! This can be imported as use `esp32_hal::prelude::*`.
 
 #[cfg(feature = "rt")]
-pub use xtensa_lx6_rt::{entry, exception};
+pub use xtensa_lx_rt::{entry, exception};
 
 pub use crate::analog::SensExt;
 pub use crate::dport::{self, Peripheral};
@@ -23,5 +23,5 @@ pub use embedded_hal::digital::v2::ToggleableOutputPin as _;
 pub use embedded_hal::prelude::*;
 pub use embedded_hal::timer::{Cancel, CountDown, Periodic};
 
-pub use xtensa_lx6::mutex::mutex_trait::prelude::*;
-pub use xtensa_lx6::mutex::CriticalSectionSpinLockMutex;
+pub use xtensa_lx::mutex::mutex_trait::prelude::*;
+pub use xtensa_lx::mutex::CriticalSectionSpinLockMutex;