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Update example
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examples/serial.rs

Lines changed: 31 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -2,55 +2,60 @@
22
#![no_main]
33
#![feature(asm)]
44

5-
use core::fmt::Write;
6-
use core::panic::PanicInfo;
7-
8-
use esp32_hal::prelude::*;
9-
10-
use esp32_hal::clock_control::sleep;
11-
use esp32_hal::dport::Split;
12-
use esp32_hal::serial::{config::Config, Pins, Serial};
13-
use esp32_hal::target;
5+
use core::{fmt::Write, panic::PanicInfo};
6+
7+
use esp32_hal::{
8+
clock_control::{sleep, ClockControl, XTAL_FREQUENCY_AUTO},
9+
dport::Split,
10+
dprintln,
11+
prelude::*,
12+
serial::{config::Config, Pins, Serial},
13+
target,
14+
timer::Timer,
15+
};
1416

1517
const BLINK_HZ: Hertz = Hertz(2);
1618

17-
#[no_mangle]
19+
#[entry]
1820
fn main() -> ! {
1921
let dp = target::Peripherals::take().expect("Failed to obtain Peripherals");
2022

21-
let mut timg0 = dp.TIMG0;
22-
let mut timg1 = dp.TIMG1;
23-
2423
let (mut dport, dport_clock_control) = dp.DPORT.split();
2524

26-
// (https://github.com/espressif/openocd-esp32/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp32.c#L431)
27-
// openocd disables the watchdog timer on halt
28-
// we will do it manually on startup
29-
disable_timg_wdts(&mut timg0, &mut timg1);
30-
31-
let clkcntrl = esp32_hal::clock_control::ClockControl::new(
25+
let clkcntrl = ClockControl::new(
3226
dp.RTCCNTL,
3327
dp.APB_CTRL,
3428
dport_clock_control,
35-
esp32_hal::clock_control::XTAL_FREQUENCY_AUTO,
29+
XTAL_FREQUENCY_AUTO,
3630
)
3731
.unwrap();
3832

3933
let (clkcntrl_config, mut watchdog) = clkcntrl.freeze().unwrap();
4034
watchdog.disable();
4135

36+
let (_, _, _, mut watchdog0) = Timer::new(dp.TIMG0, clkcntrl_config);
37+
let (_, _, _, mut watchdog1) = Timer::new(dp.TIMG1, clkcntrl_config);
38+
watchdog0.disable();
39+
watchdog1.disable();
40+
4241
let pins = dp.GPIO.split();
43-
let mut blinky = pins.gpio13.into_push_pull_output();
4442

43+
let mut blinky = pins.gpio0.into_push_pull_output();
44+
45+
// Use UART1 as example: will cause dprintln statements not to be printed
4546
let serial: Serial<_, _, _> = Serial::new(
46-
dp.UART0,
47+
dp.UART1,
4748
Pins {
4849
tx: pins.gpio1,
4950
rx: pins.gpio3,
5051
cts: None,
5152
rts: None,
5253
},
53-
Config::default(), // default configuration is 19200 baud, 8 data bits, 1 stop bit & no parity (8N1)
54+
Config {
55+
// default configuration is 19200 baud, 8 data bits, 1 stop bit & no parity (8N1)
56+
baudrate: 115200.Hz(),
57+
..Config::default()
58+
},
5459
clkcntrl_config,
5560
&mut dport,
5661
)
@@ -60,6 +65,9 @@ fn main() -> ! {
6065

6166
writeln!(tx, "\n\nESP32 Started\n\n").unwrap();
6267

68+
// line will not be printed as using UART1
69+
dprintln!("UART0\n");
70+
6371
loop {
6472
writeln!(tx, "Characters received: {:?}", rx.count()).unwrap();
6573

@@ -75,20 +83,6 @@ fn main() -> ! {
7583
}
7684
}
7785

78-
const WDT_WKEY_VALUE: u32 = 0x50D83AA1;
79-
80-
fn disable_timg_wdts(timg0: &mut target::TIMG0, timg1: &mut target::TIMG1) {
81-
timg0
82-
.wdtwprotect
83-
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
84-
timg1
85-
.wdtwprotect
86-
.write(|w| unsafe { w.bits(WDT_WKEY_VALUE) });
87-
88-
timg0.wdtconfig0.write(|w| unsafe { w.bits(0x0) });
89-
timg1.wdtconfig0.write(|w| unsafe { w.bits(0x0) });
90-
}
91-
9286
/// Basic panic handler - just loops
9387
#[panic_handler]
9488
fn panic(_info: &PanicInfo) -> ! {

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