Merge pull request #47 from arjanmels/feature-wifi

Various cleanups & extension of timer features in preparation of WiFi

Author: MabezDev

examples/adc.rs

@@ -20,7 +20,7 @@ fn main() -> ! {
     let mut timg0 = dp.TIMG0;
     let mut timg1 = dp.TIMG1;
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     // (https://github.com/espressif/openocd-esp32/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp32.c#L431)
     // openocd disables the watchdog timer on halt
@@ -50,7 +50,6 @@ fn main() -> ! {
         },
         Config::default(),
         clkcntrl_config,
-        &mut dport,
     )
     .unwrap();
 

examples/exception.rs

@@ -100,7 +100,7 @@ fn main() -> ! {
     // we will do it manually on startup
     disable_timg_wdts(&mut timg0, &mut timg1);
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     // setup clocks & watchdog
     let mut clock_control = ClockControl::new(
@@ -132,7 +132,6 @@ fn main() -> ! {
         },
         Config::default(),
         clock_control_config,
-        &mut dport,
     )
     .unwrap();
 

examples/gpio.rs

@@ -34,7 +34,7 @@ static GPIO: CriticalSectionSpinLockMutex<
 fn main() -> ! {
     let dp = target::Peripherals::take().unwrap();
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     let clkcntrl = esp32_hal::clock_control::ClockControl::new(
         dp.RTCCNTL,
@@ -73,7 +73,6 @@ fn main() -> ! {
         },
         Config::default().baudrate(115_200.Hz()),
         clkcntrl_config,
-        &mut dport,
     )
     .unwrap();
 

examples/hall.rs

@@ -20,7 +20,7 @@ fn main() -> ! {
     let mut timg0 = dp.TIMG0;
     let mut timg1 = dp.TIMG1;
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     // (https://github.com/espressif/openocd-esp32/blob/97ba3a6bb9eaa898d91df923bbedddfeaaaf28c9/src/target/esp32.c#L431)
     // openocd disables the watchdog timer on halt
@@ -50,7 +50,6 @@ fn main() -> ! {
         },
         Config::default(),
         clkcntrl_config,
-        &mut dport,
     )
     .unwrap();
 

examples/multicore.rs

@@ -32,7 +32,7 @@ fn main() -> ! {
     // we will do it manually on startup
     disable_timg_wdts(&mut timg0, &mut timg1);
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     // setup clocks & watchdog
     let mut clock_control = ClockControl::new(
@@ -71,7 +71,6 @@ fn main() -> ! {
         },
         Config::default(),
         clock_control_config,
-        &mut dport,
     )
     .unwrap();
 

examples/ram.rs

@@ -26,7 +26,7 @@ fn main() -> ! {
     // we will do it manually on startup
     disable_timg_wdts(&mut timg0, &mut timg1);
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     // setup clocks & watchdog
     let clock_control = ClockControl::new(
@@ -53,7 +53,6 @@ fn main() -> ! {
         },
         Config::default(),
         clock_control_config,
-        &mut dport,
     )
     .unwrap();
 

examples/rtccntl.rs

@@ -26,7 +26,7 @@ fn main() -> ! {
     // we will do it manually on startup
     disable_timg_wdts(&mut timg0, &mut timg1);
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     // setup clocks & watchdog
     let mut clock_control = ClockControl::new(
@@ -65,7 +65,6 @@ fn main() -> ! {
         },
         Config::default(),
         clock_control_config,
-        &mut dport,
     )
     .unwrap();
     uart0.change_baudrate(115200).unwrap();

examples/serial.rs

@@ -19,7 +19,7 @@ const BLINK_HZ: Hertz = Hertz(2);
 fn main() -> ! {
     let dp = target::Peripherals::take().expect("Failed to obtain Peripherals");
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     let clkcntrl = ClockControl::new(
         dp.RTCCNTL,
@@ -56,7 +56,6 @@ fn main() -> ! {
             ..Config::default()
         },
         clkcntrl_config,
-        &mut dport,
     )
     .unwrap();
 

examples/spi.rs

@@ -88,7 +88,7 @@ impl<
 fn main() -> ! {
     let dp = target::Peripherals::take().expect("Failed to obtain Peripherals");
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     let clkcntrl = ClockControl::new(
         dp.RTCCNTL,
@@ -123,7 +123,6 @@ fn main() -> ! {
             ..serial::config::Config::default()
         },
         clkcntrl_config,
-        &mut dport,
     )
     .unwrap();
 
@@ -145,7 +144,6 @@ fn main() -> ! {
             data_mode: spi::config::MODE_0,
         },
         clkcntrl_config,
-        &mut dport,
     )
     .unwrap();
 

examples/timer.rs

@@ -41,7 +41,7 @@ static TX: CriticalSectionSpinLockMutex<Option<esp32_hal::serial::Tx<esp32::UART
 fn main() -> ! {
     let dp = target::Peripherals::take().unwrap();
 
-    let (mut dport, dport_clock_control) = dp.DPORT.split();
+    let (_, dport_clock_control) = dp.DPORT.split();
 
     let clkcntrl = esp32_hal::clock_control::ClockControl::new(
         dp.RTCCNTL,
@@ -93,7 +93,6 @@ fn main() -> ! {
         },
         config,
         clkcntrl_config,
-        &mut dport,
     )
     .unwrap();
 

flash

@@ -243,7 +243,7 @@ then
         then
             printf "\n\n"
             # get gen_esp32part.py and create binary partition table
-            curl -s -S -f --max-time 2 -L $GENPART_SOURCE --output target/gen_esp32part.py_new
+            curl -s -S -f --max-time 5 -L $GENPART_SOURCE --output target/gen_esp32part.py_new
 
             if [ $? -ne 0 ]; then
                 if [ -f target/gen_esp32part.py ]; then
@@ -269,7 +269,7 @@ then
 
         # get bootloader.bin file 
         # (different variants exist, but only difference is flash settings which are overriden by esptool)
-        curl -s -S -f --max-time 2 -L $BOOTLOADER_SOURCE --output target/bootloader.bin_new 
+        curl -s -S -f --max-time 5 -L $BOOTLOADER_SOURCE --output target/bootloader.bin_new 
 
         if [ $? -ne 0 ]; then
             if [ -f target/bootloader.bin ]; then

memory.x

@@ -161,7 +161,23 @@ SECTIONS {
     _external_heap_start = ABSOLUTE(.);
   } > psram_seg
 
-}
+
+  /* wifi data */
+
+  .rwtext.wifi :
+  {
+    . = ALIGN(4);
+    *( .wifi0iram  .wifi0iram.*)
+    *( .wifirxiram  .wifirxiram.*)
+    *( .iram1  .iram1.*)
+  } > RWTEXT AT > RODATA
+
+  .data.wifi :
+  {
+    . = ALIGN(4);
+    *( .dram1 .dram1.*)
+  } > RWDATA AT > RODATA
+} 
 
 _external_ram_start = ABSOLUTE(ORIGIN(psram_seg));
 _external_ram_end = ABSOLUTE(ORIGIN(psram_seg)+LENGTH(psram_seg));
@@ -176,4 +192,8 @@ _stack_start_cpu0 = _stack_end_cpu1;
 _stack_end_cpu0 = _stack_start_cpu0 + STACK_SIZE;
 
 EXTERN(DefaultHandler);
+
+EXTERN(WIFI_EVENT); /* Force inclusion of WiFi libraries */
+
 INCLUDE "device.x"
+

src/alloc.rs

@@ -5,6 +5,10 @@
 //! The allocators can be safely used in a mixed fashion. (Including multiple GeneralAllocators
 //! with different thresholds)
 //!
+//! **NOTE: iram can only be accessed by aligned 32-bit accesses, as structures can indicate
+//! alignment >= 4 even when members are smaller, it cannot be used for general rust allocations.
+//! (Unless a load/store exception handler is used, but this will be very slow.)
+//!
 //! **NOTE: the default implementations of memcpy, memset etc. which are used behind the scenes use
 //! unaligned accesses.** This causes exceptions when used together with IRAM.
 //! The replacements in the mem module do handle alignment properly. They can be enable by
@@ -27,7 +31,7 @@ use core::ptr::NonNull;
 use linked_list_allocator::Heap;
 
 const DEFAULT_EXTERNAL_THRESHOLD: usize = 32 * 1024;
-const DEFAULT_USE_IRAM: bool = true;
+const DEFAULT_USE_IRAM: bool = false;
 
 /// Default allocator using a mix of memories.
 ///

src/clock_control/cpu.rs

@@ -136,12 +136,13 @@ impl super::ClockControl {
     ///
     /// The second core will start running with the function `entry`.
     pub fn start_app_core(&mut self, entry: fn() -> !) -> Result<(), Error> {
-        if self
-            .dport_control
-            .appcpu_ctrl_b()
-            .read()
-            .appcpu_clkgate_en()
-            .bit_is_set()
+        if !xtensa_lx6::is_debugger_attached()
+            && self
+                .dport_control
+                .appcpu_ctrl_b()
+                .read()
+                .appcpu_clkgate_en()
+                .bit_is_set()
         {
             return Err(Error::CoreAlreadyRunning);
         }