Various minor cleanups from code review

Co-authored-by: Scott Mabin <[email protected]>

Author: arjanmels

.cargo/config

@@ -5,8 +5,5 @@ runner = "xtensa-esp32-elf-gdb -q -x xtensa.gdb"
 rustflags = [
   "-C", "link-arg=-nostartfiles",
   "-C", "link-arg=-Wl,-Tlink.x",
-#  "-C", "target-cpu=esp32",
-#"--emit", "llvm-ir,asm",
-
 ]
 target = "xtensa-esp32-none-elf"

Cargo.toml

@@ -11,7 +11,7 @@ memcpy = false
 
 
 [features]
-default=["external_ram", "mem"]
+default=["mem"]
 
 # Place program completely in ram (needed when e.g. using only ROM bootloader, or for debugging)
 all_in_ram=[]

memory.x

@@ -176,4 +176,4 @@ _stack_start_cpu0 = _stack_end_cpu1;
 _stack_end_cpu0 = _stack_start_cpu0 + STACK_SIZE;
 
 EXTERN(DefaultHandler);
-INCLUDE "device.x"
+INCLUDE "device.x"

procmacros/src/lib.rs

@@ -1,4 +1,4 @@
-//! Internal implementation details of `xtensa-lx6-rt`.
+//! Internal implementation details of esp32-hal`.
 //!
 //! Do not use this crate directly.
 //!

src/external_ram.rs

@@ -9,7 +9,7 @@ use core::ptr::{read_volatile, write_volatile};
 static mut EXTERNAL_RAM_SIZE: core::mem::MaybeUninit<Option<usize>> =
     core::mem::MaybeUninit::uninit();
 
-/// info about teh cache to be able to trash it
+/// Info about the cache to be able to trash it
 const CACHE_LINE_SIZE: usize = 32;
 const NR_CACHE_LINES: usize = 1024;
 /// number of steps to check RAM in. 8 steps limits to 0.5MB steps