Merge pull request #29 from arjanmels/rt-split

Updated to split xtensa_lx6 and xtensa_lx6_rt

Author: MabezDev

Cargo.toml

@@ -29,7 +29,8 @@ mem=[]
 [dependencies]
 esp32-hal-proc-macros = { path = "procmacros" }
 
-xtensa-lx6-rt = { version = "0.1.0" }
+xtensa-lx6-rt = { version = "0.2.0" }
+xtensa-lx6 = { version = "0.1.0" }
 esp32 = { version = "0.4.0" }
 bare-metal = "0.2"
 nb = "0.1.2"

core

@@ -6,7 +6,7 @@ extern crate panic_halt;
 extern crate xtensa_lx6_rt;
 
 use hal::prelude::*;
-use xtensa_lx6_rt::get_cycle_count;
+use xtensa_lx6::get_cycle_count;
 
 /// The default clock source is the onboard crystal
 /// In most cases 40mhz (but can be as low as 2mhz depending on the board)

examples/blinky.rs

@@ -11,7 +11,7 @@ use esp32_hal::prelude::*;
 use esp32_hal::clock_control::{sleep, CPUSource::PLL, ClockControl};
 use esp32_hal::dport::Split;
 use esp32_hal::dprintln;
-use esp32_hal::interrupt::{Interrupt, Interrupt::*, InterruptLevel};
+use esp32_hal::interrupt::{clear_software_interrupt, Interrupt, Interrupt::*, InterruptLevel};
 use esp32_hal::serial::{config::Config, NoRx, NoTx, Serial};
 use esp32_hal::Core::PRO;
 
@@ -22,73 +22,73 @@ fn FROM_CPU_INTR0() {
     writeln!(
         TX.lock().as_mut().unwrap(),
         "  FROM_CPU_INTR0, level: {}",
-        xtensa_lx6_rt::interrupt::get_level()
+        xtensa_lx6::interrupt::get_level()
     )
     .unwrap();
-    interrupt::clear_software_interrupt(Interrupt::FROM_CPU_INTR0).unwrap();
+    clear_software_interrupt(Interrupt::FROM_CPU_INTR0).unwrap();
 }
 
 #[interrupt]
 fn FROM_CPU_INTR1() {
     writeln!(
         TX.lock().as_mut().unwrap(),
         "  Start FROM_CPU_INTR1, level: {}",
-        xtensa_lx6_rt::interrupt::get_level()
+        xtensa_lx6::interrupt::get_level()
     )
     .unwrap();
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR0).unwrap();
     interrupt::set_software_interrupt(Interrupt::FROM_CPU_INTR2).unwrap();
     writeln!(
         TX.lock().as_mut().unwrap(),
         "  End FROM_CPU_INTR1, level: {}",
-        xtensa_lx6_rt::interrupt::get_level()
+        xtensa_lx6::interrupt::get_level()
     )
     .unwrap();
-    interrupt::clear_software_interrupt(Interrupt::FROM_CPU_INTR1).unwrap();
+    clear_software_interrupt(Interrupt::FROM_CPU_INTR1).unwrap();
 }
 
 #[interrupt]
 fn FROM_CPU_INTR2() {
     writeln!(
         TX.lock().as_mut().unwrap(),
         "  FROM_CPU_INTR2, level: {}",
-        xtensa_lx6_rt::interrupt::get_level()
+        xtensa_lx6::interrupt::get_level()
     )
     .unwrap();
-    interrupt::clear_software_interrupt(Interrupt::FROM_CPU_INTR2).unwrap();
+    clear_software_interrupt(Interrupt::FROM_CPU_INTR2).unwrap();
 }
 
 #[interrupt]
 fn FROM_CPU_INTR3() {
     writeln!(
         TX.lock().as_mut().unwrap(),
         "  FROM_CPU_INTR3, level: {}",
-        xtensa_lx6_rt::interrupt::get_level()
+        xtensa_lx6::interrupt::get_level()
     )
     .unwrap();
-    interrupt::clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
+    clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
 }
 
 #[interrupt(INTERNAL_SOFTWARE_LEVEL_3_INTR)]
 fn software_level_3() {
     writeln!(
         TX.lock().as_mut().unwrap(),
         "  INTERNAL_SOFTWARE_LEVEL_3_INTR, level: {}",
-        xtensa_lx6_rt::interrupt::get_level()
+        xtensa_lx6::interrupt::get_level()
     )
     .unwrap();
-    interrupt::clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
+    clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
 }
 
 #[interrupt(INTERNAL_SOFTWARE_LEVEL_1_INTR)]
 fn random_name() {
     writeln!(
         TX.lock().as_mut().unwrap(),
         "  INTERNAL_SOFTWARE_LEVEL_1_INTR, level: {}",
-        xtensa_lx6_rt::interrupt::get_level()
+        xtensa_lx6::interrupt::get_level()
     )
     .unwrap();
-    interrupt::clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
+    clear_software_interrupt(Interrupt::FROM_CPU_INTR3).unwrap();
 }
 
 #[exception]
@@ -202,7 +202,7 @@ fn main() -> ! {
 
     loop {
         sleep(1.s());
-        xtensa_lx6_rt::interrupt::free(|_| {
+        interrupt::free(|_| {
             writeln!(TX.lock().as_mut().unwrap(), "Wait for watchdog reset").unwrap()
         });
     }

examples/exception.rs

@@ -16,6 +16,8 @@ use esp32_hal::dprintln;
 use esp32_hal::mem::{memcmp, memcpy, memcpy_reverse, memset};
 use esp32_hal::serial::{config::Config, NoRx, NoTx, Serial};
 
+use xtensa_lx6::get_cycle_count;
+
 #[macro_use]
 extern crate alloc;
 
@@ -76,11 +78,11 @@ fn main() -> ! {
     let mut dst = vec![0u8; BUF_LEN];
     let mut src = vec![0u8; BUF_LEN];
 
-    let start = xtensa_lx6_rt::get_cycle_count();
+    let start = get_cycle_count();
     for i in 0..src.len() {
         src[i] = i as u8;
     }
-    let end = xtensa_lx6_rt::get_cycle_count();
+    let end = get_cycle_count();
 
     let inittime = end.wrapping_sub(start) as f32 / ClockControlConfig {}.cpu_frequency().0 as f32;
 
@@ -130,11 +132,11 @@ fn main() -> ! {
 const REPEAT: usize = 20;
 
 fn time(output: &mut dyn core::fmt::Write, text: &str, bytes: usize, f: &dyn Fn() -> ()) {
-    let start = xtensa_lx6_rt::get_cycle_count();
+    let start = get_cycle_count();
     for _ in 0..REPEAT {
         f();
     }
-    let end = xtensa_lx6_rt::get_cycle_count();
+    let end = get_cycle_count();
 
     let time = (end - start) as f32 / ClockControlConfig {}.cpu_frequency().0 as f32;
     writeln!(
@@ -154,11 +156,11 @@ unsafe fn time_memcpy(
     len: usize,
     f: unsafe extern "C" fn(dst: *mut u8, src: *const u8, n: usize) -> *mut u8,
 ) {
-    let start = xtensa_lx6_rt::get_cycle_count();
+    let start = get_cycle_count();
     for _ in 0..REPEAT {
         f(dst as *const _ as *mut _, src as *const _ as *mut _, len);
     }
-    let end = xtensa_lx6_rt::get_cycle_count();
+    let end = get_cycle_count();
 
     let time = end.wrapping_sub(start) as f32 / ClockControlConfig {}.cpu_frequency().0 as f32;
 

examples/mem.rs

@@ -10,6 +10,9 @@ use esp32_hal::clock_control::{CPUSource, ClockControl, ClockControlConfig};
 use esp32_hal::dport::Split;
 use esp32_hal::dprintln;
 use esp32_hal::serial::{config::Config, NoRx, NoTx, Serial};
+
+use xtensa_lx6::{get_cycle_count, get_stack_pointer};
+
 const BLINK_HZ: Hertz = Hertz(1);
 
 static GLOBAL_COUNT: core::sync::atomic::AtomicU32 = core::sync::atomic::AtomicU32::new(0);
@@ -76,12 +79,7 @@ fn main() -> ! {
     )
     .unwrap();
 
-    writeln!(
-        uart0,
-        "Stack Pointer Core 0: {:08x?}",
-        xtensa_lx6_rt::get_stack_pointer()
-    )
-    .unwrap();
+    writeln!(uart0, "Stack Pointer Core 0: {:08x?}", get_stack_pointer()).unwrap();
 
     // register callback which is called when the clock is switched
     clock_control_config
@@ -131,9 +129,9 @@ fn main() -> ! {
                 x = x.wrapping_add(1);
 
                 let cycles = clock_control_config.cpu_frequency() / BLINK_HZ;
-                let start = xtensa_lx6_rt::get_cycle_count();
+                let start = get_cycle_count();
                 let mut loop_count: u32 = 0;
-                while xtensa_lx6_rt::get_cycle_count().wrapping_sub(start) < cycles {
+                while get_cycle_count().wrapping_sub(start) < cycles {
                     loop_count += 1;
                 }
 
@@ -160,15 +158,15 @@ fn cpu1_start() -> ! {
     writeln!(
         TX.lock().as_mut().unwrap(),
         "Stack Pointer Core 1: {:08x?}",
-        xtensa_lx6_rt::get_stack_pointer()
+        get_stack_pointer()
     )
     .unwrap();
 
     loop {
         let cycles = ClockControlConfig {}.cpu_frequency() / BLINK_HZ;
-        let start = xtensa_lx6_rt::get_cycle_count();
+        let start = get_cycle_count();
         let mut loop_count = 0;
-        while xtensa_lx6_rt::get_cycle_count().wrapping_sub(start) < cycles {
+        while get_cycle_count().wrapping_sub(start) < cycles {
             loop_count += 1;
         }
 
@@ -178,7 +176,7 @@ fn cpu1_start() -> ! {
 }
 
 fn print_info(loop_count: u32, spin_loop_count: u32, prev_ccount: &mut u32) {
-    let ccount = xtensa_lx6_rt::get_cycle_count();
+    let ccount = get_cycle_count();
     let ccount_diff = ccount.wrapping_sub(*prev_ccount);
 
     let total = GLOBAL_COUNT.fetch_add(ccount_diff, core::sync::atomic::Ordering::Relaxed);

examples/multicore.rs

@@ -11,6 +11,8 @@ use esp32_hal::dport::Split;
 use esp32_hal::dprintln;
 use esp32_hal::serial::{config::Config, NoRx, NoTx, Serial};
 
+use xtensa_lx6::get_program_counter;
+
 #[entry]
 fn main() -> ! {
     let dp = unsafe { esp32::Peripherals::steal() };
@@ -68,7 +70,7 @@ fn attr_none_fn(uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx, NoRx)>
         uart,
         "{:<40}: {:08x?}",
         "attr_none_fn",
-        xtensa_lx6_rt::get_program_counter()
+        get_program_counter()
     )
     .unwrap();
 }
@@ -79,7 +81,7 @@ fn attr_ram_fn(uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx, NoRx)>)
         uart,
         "{:<40}: {:08x?}",
         "attr_ram_fn",
-        xtensa_lx6_rt::get_program_counter()
+        get_program_counter()
     )
     .unwrap();
 }
@@ -90,7 +92,7 @@ fn attr_ram_fn_rtc_slow(uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx
         uart,
         "{:<40}: {:08x?}",
         "attr_ram_fn_rtc_slow",
-        xtensa_lx6_rt::get_program_counter()
+        get_program_counter()
     )
     .unwrap();
 }
@@ -101,7 +103,7 @@ fn attr_ram_fn_rtc_fast(uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx
         uart,
         "{:<40}: {:08x?}",
         "attr_ram_fn_rtc_fast",
-        xtensa_lx6_rt::get_program_counter()
+        get_program_counter()
     )
     .unwrap();
 }
@@ -204,7 +206,7 @@ fn ram_tests(uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx, NoRx)>) {
 }
 
 #[cfg(not(feature = "external_ram"))]
-fn external_ram(uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx, NoRx)>) {}
+fn external_ram(_uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx, NoRx)>) {}
 
 #[cfg(feature = "external_ram")]
 fn external_ram(uart: &mut esp32_hal::serial::Serial<esp32::UART0, (NoTx, NoRx)>) {

examples/ram.rs

@@ -116,7 +116,7 @@ fn main() -> ! {
 
                 x = x.wrapping_add(1);
 
-                let ccount = xtensa_lx6_rt::get_cycle_count();
+                let ccount = xtensa_lx6::get_cycle_count();
                 let ccount_diff = ccount.wrapping_sub(prev_ccount);
 
                 writeln!(

examples/rtccntl.rs

@@ -143,7 +143,7 @@ fn main() -> ! {
                             timer0.get_value(),
                             timer1.get_value(),
                             timer2.get_value(),
-                            xtensa_lx6_rt::get_cycle_count()
+                            xtensa_lx6::get_cycle_count()
                         )
                         .unwrap();
                         if let Ok(_) = timer1.wait() {

examples/timer.rs

@@ -172,7 +172,7 @@ pub fn ram(args: TokenStream, input: TokenStream) -> TokenStream {
 
 /// Marks a function as an interrupt handler
 ///
-/// Used to handle on of the [interrupts](interrupt/enum.Interrupt.html).
+/// Used to handle on of the [interrupts](enum.Interrupt.html).
 ///
 /// When specified between braces (`#[interrupt(example)]`) that interrupt will be used and the function
 /// can have an arbitrary name. Otherwise the name of the function must be the name of the

procmacros/src/lib.rs

@@ -26,7 +26,7 @@ use core::ptr::NonNull;
 use linked_list_allocator::Heap;
 
 use spin::{Mutex, MutexGuard};
-use xtensa_lx6_rt::interrupt;
+use xtensa_lx6::interrupt;
 
 const DEFAULT_EXTERNAL_THRESHOLD: usize = 32 * 1024;
 const DEFAULT_USE_IRAM: bool = true;

src/alloc.rs

@@ -3,6 +3,7 @@
 
 use super::Error;
 use crate::Core::{self, APP, PRO};
+use xtensa_lx6::set_stack_pointer;
 
 static mut START_CORE1_FUNCTION: Option<fn() -> !> = None;
 
@@ -118,7 +119,7 @@ impl super::ClockControl {
         }
 
         // set stack pointer to end of memory: no need to retain stack up to this point
-        xtensa_lx6_rt::set_stack_pointer(&mut _stack_end_cpu1);
+        set_stack_pointer(&mut _stack_end_cpu1);
 
         START_CORE1_FUNCTION.unwrap()();
     }