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[Test] add SplitLoopByLength test cases
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‎llvm/test/CodeGen/RISCV/RISCVSplitLoopByLength/add.ll

Lines changed: 67 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S -mtriple=riscv32-esp-unknown-elf -passes=riscv-split-loop-by-length -riscv-split-loop-by-length=false < %s | FileCheck %s
3+
; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite)
4+
define dso_local noundef i32 @dsps_add_f32_ansi(ptr noundef readonly %input1, ptr noundef readonly %input2, ptr noundef writeonly %output, i32 noundef %len, i32 noundef %step1, i32 noundef %step2, i32 noundef %step_out) local_unnamed_addr {
5+
; CHECK-LABEL: define dso_local noundef i32 @dsps_add_f32_ansi(
6+
; CHECK-SAME: ptr noundef readonly [[INPUT1:%.*]], ptr noundef readonly [[INPUT2:%.*]], ptr noundef writeonly [[OUTPUT:%.*]], i32 noundef [[LEN:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]], i32 noundef [[STEP_OUT:%.*]]) local_unnamed_addr {
7+
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[INPUT1]], null
9+
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[INPUT2]], null
10+
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
11+
; CHECK-NEXT: [[CMP4:%.*]] = icmp eq ptr [[OUTPUT]], null
12+
; CHECK-NEXT: [[OR_COND19:%.*]] = or i1 [[OR_COND]], [[CMP4]]
13+
; CHECK-NEXT: br i1 [[OR_COND19]], label [[RETURN:%.*]], label [[FOR_COND_PREHEADER:%.*]]
14+
; CHECK: for.cond.preheader:
15+
; CHECK-NEXT: [[CMP720:%.*]] = icmp sgt i32 [[LEN]], 0
16+
; CHECK-NEXT: br i1 [[CMP720]], label [[FOR_BODY:%.*]], label [[RETURN]]
17+
; CHECK: for.body:
18+
; CHECK-NEXT: [[I_021:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[FOR_COND_PREHEADER]] ]
19+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[I_021]], [[STEP1]]
20+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[INPUT1]], i32 [[MUL]]
21+
; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4
22+
; CHECK-NEXT: [[MUL8:%.*]] = mul nsw i32 [[I_021]], [[STEP2]]
23+
; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[INPUT2]], i32 [[MUL8]]
24+
; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX9]], align 4
25+
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[TMP1]]
26+
; CHECK-NEXT: [[MUL10:%.*]] = mul nsw i32 [[I_021]], [[STEP_OUT]]
27+
; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[MUL10]]
28+
; CHECK-NEXT: store float [[ADD]], ptr [[ARRAYIDX11]], align 4
29+
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_021]], 1
30+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]]
31+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[RETURN]], label [[FOR_BODY]]
32+
; CHECK: return:
33+
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 458755, [[ENTRY:%.*]] ], [ 0, [[FOR_COND_PREHEADER]] ], [ 0, [[FOR_BODY]] ]
34+
; CHECK-NEXT: ret i32 [[RETVAL_0]]
35+
;
36+
entry:
37+
%cmp = icmp eq ptr %input1, null
38+
%cmp1 = icmp eq ptr %input2, null
39+
%or.cond = or i1 %cmp, %cmp1
40+
%cmp4 = icmp eq ptr %output, null
41+
%or.cond19 = or i1 %or.cond, %cmp4
42+
br i1 %or.cond19, label %return, label %for.cond.preheader
43+
44+
for.cond.preheader: ; preds = %entry
45+
%cmp720 = icmp sgt i32 %len, 0
46+
br i1 %cmp720, label %for.body, label %return
47+
48+
for.body: ; preds = %for.body, %for.cond.preheader
49+
%i.021 = phi i32 [ %inc, %for.body ], [ 0, %for.cond.preheader ]
50+
%mul = mul nsw i32 %i.021, %step1
51+
%arrayidx = getelementptr inbounds float, ptr %input1, i32 %mul
52+
%0 = load float, ptr %arrayidx, align 4
53+
%mul8 = mul nsw i32 %i.021, %step2
54+
%arrayidx9 = getelementptr inbounds float, ptr %input2, i32 %mul8
55+
%1 = load float, ptr %arrayidx9, align 4
56+
%add = fadd float %0, %1
57+
%mul10 = mul nsw i32 %i.021, %step_out
58+
%arrayidx11 = getelementptr inbounds float, ptr %output, i32 %mul10
59+
store float %add, ptr %arrayidx11, align 4
60+
%inc = add nuw nsw i32 %i.021, 1
61+
%exitcond.not = icmp eq i32 %inc, %len
62+
br i1 %exitcond.not, label %return, label %for.body
63+
64+
return: ; preds = %for.body, %for.cond.preheader, %entry
65+
%retval.0 = phi i32 [ 458755, %entry ], [ 0, %for.cond.preheader ], [ 0, %for.body ]
66+
ret i32 %retval.0
67+
}

‎llvm/test/CodeGen/RISCV/RISCVSplitLoopByLength/addc.ll

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt -S -mtriple=riscv32-esp-unknown-elf -passes=riscv-split-loop-by-length -riscv-split-loop-by-length=false < %s | FileCheck %s
3+
; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite)
4+
define dso_local noundef i32 @dsps_addc_f32_ansi(ptr noundef readonly %input, ptr noundef writeonly %output, i32 noundef %len, float noundef %C, i32 noundef %step_in, i32 noundef %step_out) local_unnamed_addr {
5+
; CHECK-LABEL: define dso_local noundef i32 @dsps_addc_f32_ansi(
6+
; CHECK-SAME: ptr noundef readonly [[INPUT:%.*]], ptr noundef writeonly [[OUTPUT:%.*]], i32 noundef [[LEN:%.*]], float noundef [[C:%.*]], i32 noundef [[STEP_IN:%.*]], i32 noundef [[STEP_OUT:%.*]]) local_unnamed_addr {
7+
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[INPUT]], null
9+
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[OUTPUT]], null
10+
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
11+
; CHECK-NEXT: br i1 [[OR_COND]], label [[RETURN:%.*]], label [[FOR_COND_PREHEADER:%.*]]
12+
; CHECK: for.cond.preheader:
13+
; CHECK-NEXT: [[CMP412:%.*]] = icmp sgt i32 [[LEN]], 0
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; CHECK-NEXT: br i1 [[CMP412]], label [[FOR_BODY:%.*]], label [[RETURN]]
15+
; CHECK: for.body:
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; CHECK-NEXT: [[I_013:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[FOR_COND_PREHEADER]] ]
17+
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[I_013]], [[STEP_IN]]
18+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[MUL]]
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; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[C]]
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; CHECK-NEXT: [[MUL5:%.*]] = mul nsw i32 [[I_013]], [[STEP_OUT]]
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; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[MUL5]]
23+
; CHECK-NEXT: store float [[ADD]], ptr [[ARRAYIDX6]], align 4
24+
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_013]], 1
25+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]]
26+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[RETURN]], label [[FOR_BODY]]
27+
; CHECK: return:
28+
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 458755, [[ENTRY:%.*]] ], [ 0, [[FOR_COND_PREHEADER]] ], [ 0, [[FOR_BODY]] ]
29+
; CHECK-NEXT: ret i32 [[RETVAL_0]]
30+
;
31+
entry:
32+
%cmp = icmp eq ptr %input, null
33+
%cmp1 = icmp eq ptr %output, null
34+
%or.cond = or i1 %cmp, %cmp1
35+
br i1 %or.cond, label %return, label %for.cond.preheader
36+
37+
for.cond.preheader: ; preds = %entry
38+
%cmp412 = icmp sgt i32 %len, 0
39+
br i1 %cmp412, label %for.body, label %return
40+
41+
for.body: ; preds = %for.body, %for.cond.preheader
42+
%i.013 = phi i32 [ %inc, %for.body ], [ 0, %for.cond.preheader ]
43+
%mul = mul nsw i32 %i.013, %step_in
44+
%arrayidx = getelementptr inbounds float, ptr %input, i32 %mul
45+
%0 = load float, ptr %arrayidx, align 4
46+
%add = fadd float %0, %C
47+
%mul5 = mul nsw i32 %i.013, %step_out
48+
%arrayidx6 = getelementptr inbounds float, ptr %output, i32 %mul5
49+
store float %add, ptr %arrayidx6, align 4
50+
%inc = add nuw nsw i32 %i.013, 1
51+
%exitcond.not = icmp eq i32 %inc, %len
52+
br i1 %exitcond.not, label %return, label %for.body
53+
54+
return: ; preds = %for.body, %for.cond.preheader, %entry
55+
%retval.0 = phi i32 [ 458755, %entry ], [ 0, %for.cond.preheader ], [ 0, %for.body ]
56+
ret i32 %retval.0
57+
}

‎llvm/test/CodeGen/RISCV/RISCVSplitLoopByLength/biquad.ll

Lines changed: 91 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt -S -mtriple=riscv32-esp-unknown-elf -passes=riscv-split-loop-by-length -riscv-split-loop-by-length=false < %s | FileCheck %s
3+
; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite)
4+
define dso_local noundef i32 @dsps_biquad_f32_ansi(ptr nocapture noundef readonly %input, ptr nocapture noundef writeonly %output, i32 noundef %len, ptr nocapture noundef readonly %coef, ptr nocapture noundef %w) local_unnamed_addr {
5+
; CHECK-LABEL: define dso_local noundef i32 @dsps_biquad_f32_ansi(
6+
; CHECK-SAME: ptr nocapture noundef readonly [[INPUT:%.*]], ptr nocapture noundef writeonly [[OUTPUT:%.*]], i32 noundef [[LEN:%.*]], ptr nocapture noundef readonly [[COEF:%.*]], ptr nocapture noundef [[W:%.*]]) local_unnamed_addr {
7+
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: [[CMP30:%.*]] = icmp sgt i32 [[LEN]], 0
9+
; CHECK-NEXT: br i1 [[CMP30]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
10+
; CHECK: for.body.lr.ph:
11+
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[COEF]], i32 3
12+
; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[COEF]], i32 4
13+
; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[W]], i32 1
14+
; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[COEF]], i32 1
15+
; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[COEF]], i32 2
16+
; CHECK-NEXT: [[DOTPRE:%.*]] = load float, ptr [[W]], align 4
17+
; CHECK-NEXT: [[DOTPRE32:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
18+
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
19+
; CHECK: for.cond.cleanup:
20+
; CHECK-NEXT: ret i32 0
21+
; CHECK: for.body:
22+
; CHECK-NEXT: [[TMP0:%.*]] = phi float [ [[DOTPRE32]], [[FOR_BODY_LR_PH]] ], [ [[TMP12:%.*]], [[FOR_BODY]] ]
23+
; CHECK-NEXT: [[TMP1:%.*]] = phi float [ [[DOTPRE]], [[FOR_BODY_LR_PH]] ], [ [[TMP6:%.*]], [[FOR_BODY]] ]
24+
; CHECK-NEXT: [[I_031:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
25+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[INPUT]], i32 [[I_031]]
26+
; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX]], align 4
27+
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[ARRAYIDX1]], align 4
28+
; CHECK-NEXT: [[NEG:%.*]] = fneg float [[TMP3]]
29+
; CHECK-NEXT: [[TMP4:%.*]] = tail call float @llvm.fmuladd.f32(float [[NEG]], float [[TMP1]], float [[TMP2]])
30+
; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
31+
; CHECK-NEXT: [[NEG5:%.*]] = fneg float [[TMP5]]
32+
; CHECK-NEXT: [[TMP6]] = tail call float @llvm.fmuladd.f32(float [[NEG5]], float [[TMP0]], float [[TMP4]])
33+
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[COEF]], align 4
34+
; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
35+
; CHECK-NEXT: [[MUL9:%.*]] = fmul float [[TMP1]], [[TMP8]]
36+
; CHECK-NEXT: [[TMP9:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP7]], float [[TMP6]], float [[MUL9]])
37+
; CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
38+
; CHECK-NEXT: [[TMP11:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP10]], float [[TMP0]], float [[TMP9]])
39+
; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, ptr [[OUTPUT]], i32 [[I_031]]
40+
; CHECK-NEXT: store float [[TMP11]], ptr [[ARRAYIDX12]], align 4
41+
; CHECK-NEXT: [[TMP12]] = load float, ptr [[W]], align 4
42+
; CHECK-NEXT: store float [[TMP12]], ptr [[ARRAYIDX4]], align 4
43+
; CHECK-NEXT: store float [[TMP6]], ptr [[W]], align 4
44+
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_031]], 1
45+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]]
46+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
47+
;
48+
entry:
49+
%cmp30 = icmp sgt i32 %len, 0
50+
br i1 %cmp30, label %for.body.lr.ph, label %for.cond.cleanup
51+
52+
for.body.lr.ph: ; preds = %entry
53+
%arrayidx1 = getelementptr inbounds float, ptr %coef, i32 3
54+
%arrayidx3 = getelementptr inbounds float, ptr %coef, i32 4
55+
%arrayidx4 = getelementptr inbounds float, ptr %w, i32 1
56+
%arrayidx7 = getelementptr inbounds float, ptr %coef, i32 1
57+
%arrayidx10 = getelementptr inbounds float, ptr %coef, i32 2
58+
%.pre = load float, ptr %w, align 4
59+
%.pre32 = load float, ptr %arrayidx4, align 4
60+
br label %for.body
61+
62+
for.cond.cleanup: ; preds = %for.body, %entry
63+
ret i32 0
64+
65+
for.body: ; preds = %for.body, %for.body.lr.ph
66+
%0 = phi float [ %.pre32, %for.body.lr.ph ], [ %12, %for.body ]
67+
%1 = phi float [ %.pre, %for.body.lr.ph ], [ %6, %for.body ]
68+
%i.031 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
69+
%arrayidx = getelementptr inbounds float, ptr %input, i32 %i.031
70+
%2 = load float, ptr %arrayidx, align 4
71+
%3 = load float, ptr %arrayidx1, align 4
72+
%neg = fneg float %3
73+
%4 = tail call float @llvm.fmuladd.f32(float %neg, float %1, float %2)
74+
%5 = load float, ptr %arrayidx3, align 4
75+
%neg5 = fneg float %5
76+
%6 = tail call float @llvm.fmuladd.f32(float %neg5, float %0, float %4)
77+
%7 = load float, ptr %coef, align 4
78+
%8 = load float, ptr %arrayidx7, align 4
79+
%mul9 = fmul float %1, %8
80+
%9 = tail call float @llvm.fmuladd.f32(float %7, float %6, float %mul9)
81+
%10 = load float, ptr %arrayidx10, align 4
82+
%11 = tail call float @llvm.fmuladd.f32(float %10, float %0, float %9)
83+
%arrayidx12 = getelementptr inbounds float, ptr %output, i32 %i.031
84+
store float %11, ptr %arrayidx12, align 4
85+
%12 = load float, ptr %w, align 4
86+
store float %12, ptr %arrayidx4, align 4
87+
store float %6, ptr %w, align 4
88+
%inc = add nuw nsw i32 %i.031, 1
89+
%exitcond.not = icmp eq i32 %inc, %len
90+
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
91+
}

‎llvm/test/CodeGen/RISCV/RISCVSplitLoopByLength/dotprod.ll

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt -S -mtriple=riscv32-esp-unknown-elf -passes=riscv-split-loop-by-length -riscv-split-loop-by-length=false < %s | FileCheck %s
3+
; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite)
4+
define dso_local noundef i32 @dsps_dotprod_f32_ansi(ptr nocapture noundef readonly %src1, ptr nocapture noundef readonly %src2, ptr nocapture noundef writeonly %dest, i32 noundef %len) local_unnamed_addr {
5+
; CHECK-LABEL: define dso_local noundef i32 @dsps_dotprod_f32_ansi(
6+
; CHECK-SAME: ptr nocapture noundef readonly [[SRC1:%.*]], ptr nocapture noundef readonly [[SRC2:%.*]], ptr nocapture noundef writeonly [[DEST:%.*]], i32 noundef [[LEN:%.*]]) local_unnamed_addr {
7+
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[LEN]], 0
9+
; CHECK-NEXT: br i1 [[CMP6]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
10+
; CHECK: for.cond.cleanup:
11+
; CHECK-NEXT: [[ACC_0_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[FOR_BODY]] ]
12+
; CHECK-NEXT: store float [[ACC_0_LCSSA]], ptr [[DEST]], align 4
13+
; CHECK-NEXT: ret i32 0
14+
; CHECK: for.body:
15+
; CHECK-NEXT: [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
16+
; CHECK-NEXT: [[ACC_07:%.*]] = phi float [ [[TMP2]], [[FOR_BODY]] ], [ 0.000000e+00, [[ENTRY]] ]
17+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[SRC1]], i32 [[I_08]]
18+
; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4
19+
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[SRC2]], i32 [[I_08]]
20+
; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX1]], align 4
21+
; CHECK-NEXT: [[TMP2]] = tail call float @llvm.fmuladd.f32(float [[TMP0]], float [[TMP1]], float [[ACC_07]])
22+
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
23+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]]
24+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
25+
;
26+
entry:
27+
%cmp6 = icmp sgt i32 %len, 0
28+
br i1 %cmp6, label %for.body, label %for.cond.cleanup
29+
30+
for.cond.cleanup: ; preds = %for.body, %entry
31+
%acc.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %2, %for.body ]
32+
store float %acc.0.lcssa, ptr %dest, align 4
33+
ret i32 0
34+
35+
for.body: ; preds = %for.body, %entry
36+
%i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
37+
%acc.07 = phi float [ %2, %for.body ], [ 0.000000e+00, %entry ]
38+
%arrayidx = getelementptr inbounds float, ptr %src1, i32 %i.08
39+
%0 = load float, ptr %arrayidx, align 4
40+
%arrayidx1 = getelementptr inbounds float, ptr %src2, i32 %i.08
41+
%1 = load float, ptr %arrayidx1, align 4
42+
%2 = tail call float @llvm.fmuladd.f32(float %0, float %1, float %acc.07)
43+
%inc = add nuw nsw i32 %i.08, 1
44+
%exitcond.not = icmp eq i32 %inc, %len
45+
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
46+
}

‎llvm/test/CodeGen/RISCV/RISCVSplitLoopByLength/dotprode.ll

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt -S -mtriple=riscv32-esp-unknown-elf -passes=riscv-split-loop-by-length -riscv-split-loop-by-length=false < %s | FileCheck %s
3+
; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite)
4+
define dso_local noundef i32 @dsps_dotprode_f32_ansi(ptr nocapture noundef readonly %src1, ptr nocapture noundef readonly %src2, ptr nocapture noundef writeonly %dest, i32 noundef %len, i32 noundef %step1, i32 noundef %step2) local_unnamed_addr {
5+
; CHECK-LABEL: define dso_local noundef i32 @dsps_dotprode_f32_ansi(
6+
; CHECK-SAME: ptr nocapture noundef readonly [[SRC1:%.*]], ptr nocapture noundef readonly [[SRC2:%.*]], ptr nocapture noundef writeonly [[DEST:%.*]], i32 noundef [[LEN:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]]) local_unnamed_addr {
7+
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[LEN]], 0
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; CHECK-NEXT: br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: [[ACC_0_LCSSA:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: store float [[ACC_0_LCSSA]], ptr [[DEST]], align 4
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; CHECK-NEXT: ret i32 0
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; CHECK: for.body:
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; CHECK-NEXT: [[I_010:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
16+
; CHECK-NEXT: [[ACC_09:%.*]] = phi float [ [[TMP2]], [[FOR_BODY]] ], [ 0.000000e+00, [[ENTRY]] ]
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[I_010]], [[STEP1]]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[SRC1]], i32 [[MUL]]
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; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[MUL1:%.*]] = mul nsw i32 [[I_010]], [[STEP2]]
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; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[SRC2]], i32 [[MUL1]]
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; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
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; CHECK-NEXT: [[TMP2]] = tail call float @llvm.fmuladd.f32(float [[TMP0]], float [[TMP1]], float [[ACC_09]])
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; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_010]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
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;
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entry:
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%cmp8 = icmp sgt i32 %len, 0
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br i1 %cmp8, label %for.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body, %entry
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%acc.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %2, %for.body ]
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store float %acc.0.lcssa, ptr %dest, align 4
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ret i32 0
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for.body: ; preds = %for.body, %entry
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%i.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%acc.09 = phi float [ %2, %for.body ], [ 0.000000e+00, %entry ]
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%mul = mul nsw i32 %i.010, %step1
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%arrayidx = getelementptr inbounds float, ptr %src1, i32 %mul
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%0 = load float, ptr %arrayidx, align 4
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%mul1 = mul nsw i32 %i.010, %step2
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%arrayidx2 = getelementptr inbounds float, ptr %src2, i32 %mul1
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%1 = load float, ptr %arrayidx2, align 4
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%2 = tail call float @llvm.fmuladd.f32(float %0, float %1, float %acc.09)
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%inc = add nuw nsw i32 %i.010, 1
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%exitcond.not = icmp eq i32 %inc, %len
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}

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