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[AArch64] Fix over-eager early-exit in load-store combiner
Fix early-exit analysis for memory operation pairing when operations are not emitted in ascending order. Reviewers: mcrosier, t.p.northover Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D28251 llvm-svn: 291008
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llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

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@@ -1470,6 +1470,9 @@ bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
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bool IsUnscaled = TII->isUnscaledLdSt(MI);
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int Offset = getLdStOffsetOp(MI).getImm();
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int OffsetStride = IsUnscaled ? getMemScale(MI) : 1;
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// Allow one more for offset.
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if (Offset > 0)
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Offset -= OffsetStride;
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if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride))
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return false;
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; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -disable-lsr -verify-machineinstrs -enable-misched=false -enable-post-misched=false -o - %s | FileCheck %s
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define i64 @test(i64* %a) nounwind {
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; CHECK: ldp x{{[0-9]+}}, x{{[0-9]+}}
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; CHECK-NOT: ldr
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%p1 = getelementptr inbounds i64, i64* %a, i32 64
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%tmp1 = load i64, i64* %p1, align 2
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%p2 = getelementptr inbounds i64, i64* %a, i32 63
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%tmp2 = load i64, i64* %p2, align 2
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%tmp3 = add i64 %tmp1, %tmp2
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ret i64 %tmp3
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}

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