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[RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb. (llvm#144571)
We know that vlenb is a multiple of RVVBytesPerBlock so we aren't shifting out any non-zero bits.
1 parent 190be5b commit 57177c1

11 files changed

+179
-199
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7353,20 +7353,25 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
73537353
uint64_t Val = Op.getConstantOperandVal(0);
73547354
if (isPowerOf2_64(Val)) {
73557355
uint64_t Log2 = Log2_64(Val);
7356-
if (Log2 < 3)
7356+
if (Log2 < 3) {
7357+
SDNodeFlags Flags;
7358+
Flags.setExact(true);
73577359
Res = DAG.getNode(ISD::SRL, DL, XLenVT, Res,
7358-
DAG.getConstant(3 - Log2, DL, VT));
7359-
else if (Log2 > 3)
7360+
DAG.getConstant(3 - Log2, DL, XLenVT), Flags);
7361+
} else if (Log2 > 3) {
73607362
Res = DAG.getNode(ISD::SHL, DL, XLenVT, Res,
73617363
DAG.getConstant(Log2 - 3, DL, XLenVT));
7364+
}
73627365
} else if ((Val % 8) == 0) {
73637366
// If the multiplier is a multiple of 8, scale it down to avoid needing
73647367
// to shift the VLENB value.
73657368
Res = DAG.getNode(ISD::MUL, DL, XLenVT, Res,
73667369
DAG.getConstant(Val / 8, DL, XLenVT));
73677370
} else {
7371+
SDNodeFlags Flags;
7372+
Flags.setExact(true);
73687373
SDValue VScale = DAG.getNode(ISD::SRL, DL, XLenVT, Res,
7369-
DAG.getConstant(3, DL, XLenVT));
7374+
DAG.getConstant(3, DL, XLenVT), Flags);
73707375
Res = DAG.getNode(ISD::MUL, DL, XLenVT, VScale,
73717376
DAG.getConstant(Val, DL, XLenVT));
73727377
}

‎llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -290,8 +290,7 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {
290290
; CHECK-LABEL: extract_nxv32i8_nxv2i8_6:
291291
; CHECK: # %bb.0:
292292
; CHECK-NEXT: csrr a0, vlenb
293-
; CHECK-NEXT: srli a1, a0, 3
294-
; CHECK-NEXT: slli a1, a1, 1
293+
; CHECK-NEXT: srli a1, a0, 2
295294
; CHECK-NEXT: sub a0, a0, a1
296295
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
297296
; CHECK-NEXT: vslidedown.vx v8, v8, a0
@@ -314,8 +313,7 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {
314313
; CHECK-LABEL: extract_nxv32i8_nxv2i8_22:
315314
; CHECK: # %bb.0:
316315
; CHECK-NEXT: csrr a0, vlenb
317-
; CHECK-NEXT: srli a1, a0, 3
318-
; CHECK-NEXT: slli a1, a1, 1
316+
; CHECK-NEXT: srli a1, a0, 2
319317
; CHECK-NEXT: sub a0, a0, a1
320318
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
321319
; CHECK-NEXT: vslidedown.vx v8, v10, a0
@@ -341,9 +339,9 @@ define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) {
341339
; CHECK-LABEL: extract_nxv4i8_nxv1i8_3:
342340
; CHECK: # %bb.0:
343341
; CHECK-NEXT: csrr a0, vlenb
344-
; CHECK-NEXT: srli a0, a0, 3
345-
; CHECK-NEXT: slli a1, a0, 1
346-
; CHECK-NEXT: add a0, a1, a0
342+
; CHECK-NEXT: srli a1, a0, 3
343+
; CHECK-NEXT: srli a0, a0, 2
344+
; CHECK-NEXT: add a0, a0, a1
347345
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
348346
; CHECK-NEXT: vslidedown.vx v8, v8, a0
349347
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -257,9 +257,9 @@ define i32 @vector_length_vf3_i32(i32 zeroext %tc) {
257257
; RV32-LABEL: vector_length_vf3_i32:
258258
; RV32: # %bb.0:
259259
; RV32-NEXT: csrr a1, vlenb
260-
; RV32-NEXT: srli a1, a1, 3
261-
; RV32-NEXT: slli a2, a1, 1
262-
; RV32-NEXT: add a1, a2, a1
260+
; RV32-NEXT: srli a2, a1, 3
261+
; RV32-NEXT: srli a1, a1, 2
262+
; RV32-NEXT: add a1, a1, a2
263263
; RV32-NEXT: bltu a0, a1, .LBB22_2
264264
; RV32-NEXT: # %bb.1:
265265
; RV32-NEXT: mv a0, a1
@@ -270,9 +270,9 @@ define i32 @vector_length_vf3_i32(i32 zeroext %tc) {
270270
; RV64: # %bb.0:
271271
; RV64-NEXT: sext.w a0, a0
272272
; RV64-NEXT: csrr a1, vlenb
273-
; RV64-NEXT: srli a1, a1, 3
274-
; RV64-NEXT: slli a2, a1, 1
275-
; RV64-NEXT: add a1, a2, a1
273+
; RV64-NEXT: srli a2, a1, 3
274+
; RV64-NEXT: srli a1, a1, 2
275+
; RV64-NEXT: add a1, a1, a2
276276
; RV64-NEXT: bltu a0, a1, .LBB22_2
277277
; RV64-NEXT: # %bb.1:
278278
; RV64-NEXT: mv a0, a1
@@ -286,9 +286,9 @@ define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {
286286
; RV32-LABEL: vector_length_vf3_XLen:
287287
; RV32: # %bb.0:
288288
; RV32-NEXT: csrr a1, vlenb
289-
; RV32-NEXT: srli a1, a1, 3
290-
; RV32-NEXT: slli a2, a1, 1
291-
; RV32-NEXT: add a1, a2, a1
289+
; RV32-NEXT: srli a2, a1, 3
290+
; RV32-NEXT: srli a1, a1, 2
291+
; RV32-NEXT: add a1, a1, a2
292292
; RV32-NEXT: bltu a0, a1, .LBB23_2
293293
; RV32-NEXT: # %bb.1:
294294
; RV32-NEXT: mv a0, a1
@@ -299,9 +299,9 @@ define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {
299299
; RV64: # %bb.0:
300300
; RV64-NEXT: sext.w a0, a0
301301
; RV64-NEXT: csrr a1, vlenb
302-
; RV64-NEXT: srli a1, a1, 3
303-
; RV64-NEXT: slli a2, a1, 1
304-
; RV64-NEXT: add a1, a2, a1
302+
; RV64-NEXT: srli a2, a1, 3
303+
; RV64-NEXT: srli a1, a1, 2
304+
; RV64-NEXT: add a1, a1, a2
305305
; RV64-NEXT: bltu a0, a1, .LBB23_2
306306
; RV64-NEXT: # %bb.1:
307307
; RV64-NEXT: mv a0, a1

‎llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -78,12 +78,12 @@ define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale
7878
; CHECK-LABEL: insert_nxv1i8_nxv4i8_3:
7979
; CHECK: # %bb.0:
8080
; CHECK-NEXT: csrr a0, vlenb
81-
; CHECK-NEXT: srli a0, a0, 3
82-
; CHECK-NEXT: slli a1, a0, 1
83-
; CHECK-NEXT: add a1, a1, a0
84-
; CHECK-NEXT: add a0, a1, a0
85-
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
86-
; CHECK-NEXT: vslideup.vx v8, v9, a1
81+
; CHECK-NEXT: srli a1, a0, 3
82+
; CHECK-NEXT: srli a0, a0, 2
83+
; CHECK-NEXT: add a0, a0, a1
84+
; CHECK-NEXT: add a1, a0, a1
85+
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
86+
; CHECK-NEXT: vslideup.vx v8, v9, a0
8787
; CHECK-NEXT: ret
8888
%v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
8989
ret <vscale x 4 x i8> %v
@@ -309,12 +309,12 @@ define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vsc
309309
; CHECK-LABEL: insert_nxv16i8_nxv1i8_3:
310310
; CHECK: # %bb.0:
311311
; CHECK-NEXT: csrr a0, vlenb
312-
; CHECK-NEXT: srli a0, a0, 3
313-
; CHECK-NEXT: slli a1, a0, 1
314-
; CHECK-NEXT: add a1, a1, a0
315-
; CHECK-NEXT: add a0, a1, a0
316-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
317-
; CHECK-NEXT: vslideup.vx v8, v10, a1
312+
; CHECK-NEXT: srli a1, a0, 3
313+
; CHECK-NEXT: srli a0, a0, 2
314+
; CHECK-NEXT: add a0, a0, a1
315+
; CHECK-NEXT: add a1, a0, a1
316+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
317+
; CHECK-NEXT: vslideup.vx v8, v10, a0
318318
; CHECK-NEXT: ret
319319
%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
320320
ret <vscale x 16 x i8> %v

‎llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ define <vscale x 3 x i8> @load_nxv3i8(ptr %ptr) {
88
; CHECK-LABEL: load_nxv3i8:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: csrr a1, vlenb
11-
; CHECK-NEXT: srli a1, a1, 3
12-
; CHECK-NEXT: slli a2, a1, 1
13-
; CHECK-NEXT: add a1, a2, a1
11+
; CHECK-NEXT: srli a2, a1, 3
12+
; CHECK-NEXT: srli a1, a1, 2
13+
; CHECK-NEXT: add a1, a1, a2
1414
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
1515
; CHECK-NEXT: vle8.v v8, (a0)
1616
; CHECK-NEXT: ret
@@ -22,9 +22,9 @@ define <vscale x 5 x half> @load_nxv5f16(ptr %ptr) {
2222
; CHECK-LABEL: load_nxv5f16:
2323
; CHECK: # %bb.0:
2424
; CHECK-NEXT: csrr a1, vlenb
25-
; CHECK-NEXT: srli a1, a1, 3
26-
; CHECK-NEXT: slli a2, a1, 2
27-
; CHECK-NEXT: add a1, a2, a1
25+
; CHECK-NEXT: srli a2, a1, 3
26+
; CHECK-NEXT: srli a1, a1, 1
27+
; CHECK-NEXT: add a1, a1, a2
2828
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2929
; CHECK-NEXT: vle16.v v8, (a0)
3030
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ define void @store_nxv3i8(<vscale x 3 x i8> %val, ptr %ptr) {
88
; CHECK-LABEL: store_nxv3i8:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: csrr a1, vlenb
11-
; CHECK-NEXT: srli a1, a1, 3
12-
; CHECK-NEXT: slli a2, a1, 1
13-
; CHECK-NEXT: add a1, a2, a1
11+
; CHECK-NEXT: srli a2, a1, 3
12+
; CHECK-NEXT: srli a1, a1, 2
13+
; CHECK-NEXT: add a1, a1, a2
1414
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
1515
; CHECK-NEXT: vse8.v v8, (a0)
1616
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/stepvector.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -637,21 +637,21 @@ define <vscale x 16 x i64> @mul_bigimm_stepvector_nxv16i64() {
637637
; RV32-NEXT: lui a1, 797989
638638
; RV32-NEXT: csrr a2, vlenb
639639
; RV32-NEXT: lui a3, 11557
640-
; RV32-NEXT: lui a4, 92455
641640
; RV32-NEXT: addi a1, a1, -683
642-
; RV32-NEXT: addi a3, a3, -683
641+
; RV32-NEXT: srli a4, a2, 2
643642
; RV32-NEXT: sw a1, 8(sp)
644643
; RV32-NEXT: sw a0, 12(sp)
645-
; RV32-NEXT: srli a0, a2, 3
646-
; RV32-NEXT: addi a1, a4, -1368
647-
; RV32-NEXT: mul a2, a2, a3
648-
; RV32-NEXT: mulhu a1, a0, a1
649-
; RV32-NEXT: slli a3, a0, 1
650-
; RV32-NEXT: slli a0, a0, 6
651-
; RV32-NEXT: sub a0, a0, a3
644+
; RV32-NEXT: slli a0, a2, 3
645+
; RV32-NEXT: sub a0, a0, a4
646+
; RV32-NEXT: lui a1, 92455
647+
; RV32-NEXT: addi a3, a3, -683
648+
; RV32-NEXT: mul a3, a2, a3
649+
; RV32-NEXT: srli a2, a2, 3
650+
; RV32-NEXT: addi a1, a1, -1368
651+
; RV32-NEXT: mulhu a1, a2, a1
652652
; RV32-NEXT: add a0, a1, a0
653653
; RV32-NEXT: addi a1, sp, 8
654-
; RV32-NEXT: sw a2, 0(sp)
654+
; RV32-NEXT: sw a3, 0(sp)
655655
; RV32-NEXT: sw a0, 4(sp)
656656
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
657657
; RV32-NEXT: vlse64.v v8, (a1), zero

‎llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll

Lines changed: 21 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2240,20 +2240,19 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
22402240
; CHECK-RV32-LABEL: vand_vx_loop_hoisted_not:
22412241
; CHECK-RV32: # %bb.0: # %entry
22422242
; CHECK-RV32-NEXT: csrr a4, vlenb
2243-
; CHECK-RV32-NEXT: srli a3, a4, 3
2244-
; CHECK-RV32-NEXT: li a2, 64
2243+
; CHECK-RV32-NEXT: srli a2, a4, 3
2244+
; CHECK-RV32-NEXT: li a3, 64
22452245
; CHECK-RV32-NEXT: not a1, a1
2246-
; CHECK-RV32-NEXT: bgeu a2, a3, .LBB98_2
2246+
; CHECK-RV32-NEXT: bgeu a3, a2, .LBB98_2
22472247
; CHECK-RV32-NEXT: # %bb.1:
22482248
; CHECK-RV32-NEXT: li a3, 0
22492249
; CHECK-RV32-NEXT: li a2, 0
22502250
; CHECK-RV32-NEXT: j .LBB98_5
22512251
; CHECK-RV32-NEXT: .LBB98_2: # %vector.ph
22522252
; CHECK-RV32-NEXT: li a2, 0
2253-
; CHECK-RV32-NEXT: slli a3, a3, 2
2254-
; CHECK-RV32-NEXT: neg a3, a3
2255-
; CHECK-RV32-NEXT: andi a3, a3, 256
22562253
; CHECK-RV32-NEXT: srli a4, a4, 1
2254+
; CHECK-RV32-NEXT: neg a3, a4
2255+
; CHECK-RV32-NEXT: andi a3, a3, 256
22572256
; CHECK-RV32-NEXT: li a6, 0
22582257
; CHECK-RV32-NEXT: li a5, 0
22592258
; CHECK-RV32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2300,10 +2299,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
23002299
; CHECK-RV64-NEXT: li a2, 0
23012300
; CHECK-RV64-NEXT: j .LBB98_5
23022301
; CHECK-RV64-NEXT: .LBB98_2: # %vector.ph
2303-
; CHECK-RV64-NEXT: slli a2, a2, 2
2304-
; CHECK-RV64-NEXT: negw a2, a2
2305-
; CHECK-RV64-NEXT: andi a2, a2, 256
23062302
; CHECK-RV64-NEXT: srli a3, a4, 1
2303+
; CHECK-RV64-NEXT: negw a2, a3
2304+
; CHECK-RV64-NEXT: andi a2, a2, 256
23072305
; CHECK-RV64-NEXT: slli a4, a4, 1
23082306
; CHECK-RV64-NEXT: mv a5, a0
23092307
; CHECK-RV64-NEXT: mv a6, a2
@@ -2335,19 +2333,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
23352333
; CHECK-ZVKB-NOZBB32-LABEL: vand_vx_loop_hoisted_not:
23362334
; CHECK-ZVKB-NOZBB32: # %bb.0: # %entry
23372335
; CHECK-ZVKB-NOZBB32-NEXT: csrr a4, vlenb
2338-
; CHECK-ZVKB-NOZBB32-NEXT: srli a3, a4, 3
2339-
; CHECK-ZVKB-NOZBB32-NEXT: li a2, 64
2340-
; CHECK-ZVKB-NOZBB32-NEXT: bgeu a2, a3, .LBB98_2
2336+
; CHECK-ZVKB-NOZBB32-NEXT: srli a2, a4, 3
2337+
; CHECK-ZVKB-NOZBB32-NEXT: li a3, 64
2338+
; CHECK-ZVKB-NOZBB32-NEXT: bgeu a3, a2, .LBB98_2
23412339
; CHECK-ZVKB-NOZBB32-NEXT: # %bb.1:
23422340
; CHECK-ZVKB-NOZBB32-NEXT: li a3, 0
23432341
; CHECK-ZVKB-NOZBB32-NEXT: li a2, 0
23442342
; CHECK-ZVKB-NOZBB32-NEXT: j .LBB98_5
23452343
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_2: # %vector.ph
23462344
; CHECK-ZVKB-NOZBB32-NEXT: li a2, 0
2347-
; CHECK-ZVKB-NOZBB32-NEXT: slli a3, a3, 2
2348-
; CHECK-ZVKB-NOZBB32-NEXT: neg a3, a3
2349-
; CHECK-ZVKB-NOZBB32-NEXT: andi a3, a3, 256
23502345
; CHECK-ZVKB-NOZBB32-NEXT: srli a4, a4, 1
2346+
; CHECK-ZVKB-NOZBB32-NEXT: neg a3, a4
2347+
; CHECK-ZVKB-NOZBB32-NEXT: andi a3, a3, 256
23512348
; CHECK-ZVKB-NOZBB32-NEXT: li a6, 0
23522349
; CHECK-ZVKB-NOZBB32-NEXT: li a5, 0
23532350
; CHECK-ZVKB-NOZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2395,10 +2392,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
23952392
; CHECK-ZVKB-NOZBB64-NEXT: li a2, 0
23962393
; CHECK-ZVKB-NOZBB64-NEXT: j .LBB98_5
23972394
; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_2: # %vector.ph
2398-
; CHECK-ZVKB-NOZBB64-NEXT: slli a2, a2, 2
2399-
; CHECK-ZVKB-NOZBB64-NEXT: negw a2, a2
2400-
; CHECK-ZVKB-NOZBB64-NEXT: andi a2, a2, 256
24012395
; CHECK-ZVKB-NOZBB64-NEXT: srli a3, a4, 1
2396+
; CHECK-ZVKB-NOZBB64-NEXT: negw a2, a3
2397+
; CHECK-ZVKB-NOZBB64-NEXT: andi a2, a2, 256
24022398
; CHECK-ZVKB-NOZBB64-NEXT: slli a4, a4, 1
24032399
; CHECK-ZVKB-NOZBB64-NEXT: mv a5, a0
24042400
; CHECK-ZVKB-NOZBB64-NEXT: mv a6, a2
@@ -2431,19 +2427,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
24312427
; CHECK-ZVKB-ZBB32-LABEL: vand_vx_loop_hoisted_not:
24322428
; CHECK-ZVKB-ZBB32: # %bb.0: # %entry
24332429
; CHECK-ZVKB-ZBB32-NEXT: csrr a4, vlenb
2434-
; CHECK-ZVKB-ZBB32-NEXT: srli a3, a4, 3
2435-
; CHECK-ZVKB-ZBB32-NEXT: li a2, 64
2436-
; CHECK-ZVKB-ZBB32-NEXT: bgeu a2, a3, .LBB98_2
2430+
; CHECK-ZVKB-ZBB32-NEXT: srli a2, a4, 3
2431+
; CHECK-ZVKB-ZBB32-NEXT: li a3, 64
2432+
; CHECK-ZVKB-ZBB32-NEXT: bgeu a3, a2, .LBB98_2
24372433
; CHECK-ZVKB-ZBB32-NEXT: # %bb.1:
24382434
; CHECK-ZVKB-ZBB32-NEXT: li a3, 0
24392435
; CHECK-ZVKB-ZBB32-NEXT: li a2, 0
24402436
; CHECK-ZVKB-ZBB32-NEXT: j .LBB98_5
24412437
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_2: # %vector.ph
24422438
; CHECK-ZVKB-ZBB32-NEXT: li a2, 0
2443-
; CHECK-ZVKB-ZBB32-NEXT: slli a3, a3, 2
2444-
; CHECK-ZVKB-ZBB32-NEXT: neg a3, a3
2445-
; CHECK-ZVKB-ZBB32-NEXT: andi a3, a3, 256
24462439
; CHECK-ZVKB-ZBB32-NEXT: srli a4, a4, 1
2440+
; CHECK-ZVKB-ZBB32-NEXT: neg a3, a4
2441+
; CHECK-ZVKB-ZBB32-NEXT: andi a3, a3, 256
24472442
; CHECK-ZVKB-ZBB32-NEXT: li a6, 0
24482443
; CHECK-ZVKB-ZBB32-NEXT: li a5, 0
24492444
; CHECK-ZVKB-ZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2489,10 +2484,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
24892484
; CHECK-ZVKB-ZBB64-NEXT: li a2, 0
24902485
; CHECK-ZVKB-ZBB64-NEXT: j .LBB98_5
24912486
; CHECK-ZVKB-ZBB64-NEXT: .LBB98_2: # %vector.ph
2492-
; CHECK-ZVKB-ZBB64-NEXT: slli a2, a2, 2
2493-
; CHECK-ZVKB-ZBB64-NEXT: negw a2, a2
2494-
; CHECK-ZVKB-ZBB64-NEXT: andi a2, a2, 256
24952487
; CHECK-ZVKB-ZBB64-NEXT: srli a3, a4, 1
2488+
; CHECK-ZVKB-ZBB64-NEXT: negw a2, a3
2489+
; CHECK-ZVKB-ZBB64-NEXT: andi a2, a2, 256
24962490
; CHECK-ZVKB-ZBB64-NEXT: slli a4, a4, 1
24972491
; CHECK-ZVKB-ZBB64-NEXT: mv a5, a0
24982492
; CHECK-ZVKB-ZBB64-NEXT: mv a6, a2

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -338,16 +338,14 @@ define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} @v
338338
; CHECK-NEXT: vsetvli zero, a3, e8, mf2, tu, ma
339339
; CHECK-NEXT: vslideup.vx v10, v9, a1
340340
; CHECK-NEXT: vslideup.vx v8, v12, a1
341-
; CHECK-NEXT: slli a3, a1, 1
341+
; CHECK-NEXT: add a3, a0, a0
342+
; CHECK-NEXT: add a1, a4, a1
342343
; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
343344
; CHECK-NEXT: vslideup.vx v10, v11, a2
344345
; CHECK-NEXT: vslideup.vx v8, v13, a2
345-
; CHECK-NEXT: add a2, a0, a0
346-
; CHECK-NEXT: add a3, a3, a1
347-
; CHECK-NEXT: add a1, a3, a1
348346
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
349-
; CHECK-NEXT: vslideup.vx v8, v14, a3
350-
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma
347+
; CHECK-NEXT: vslideup.vx v8, v14, a4
348+
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
351349
; CHECK-NEXT: vslideup.vx v8, v10, a0
352350
; CHECK-NEXT: addi a0, sp, 16
353351
; CHECK-NEXT: vs1r.v v8, (a0)
@@ -381,20 +379,18 @@ define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2
381379
; CHECK-NEXT: srli a0, a0, 1
382380
; CHECK-NEXT: add a3, a1, a1
383381
; CHECK-NEXT: add a4, a2, a1
384-
; CHECK-NEXT: slli a5, a1, 1
385-
; CHECK-NEXT: add a6, a0, a0
382+
; CHECK-NEXT: add a5, a0, a0
386383
; CHECK-NEXT: vsetvli zero, a3, e8, mf2, tu, ma
387384
; CHECK-NEXT: vslideup.vx v10, v9, a1
388-
; CHECK-NEXT: add a5, a5, a1
389385
; CHECK-NEXT: vslideup.vx v8, v13, a1
386+
; CHECK-NEXT: add a1, a4, a1
390387
; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
391388
; CHECK-NEXT: vslideup.vx v10, v11, a2
392-
; CHECK-NEXT: add a1, a5, a1
393389
; CHECK-NEXT: vslideup.vx v8, v14, a2
394390
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
395-
; CHECK-NEXT: vslideup.vx v10, v12, a5
396-
; CHECK-NEXT: vslideup.vx v8, v15, a5
397-
; CHECK-NEXT: vsetvli zero, a6, e8, m1, ta, ma
391+
; CHECK-NEXT: vslideup.vx v10, v12, a4
392+
; CHECK-NEXT: vslideup.vx v8, v15, a4
393+
; CHECK-NEXT: vsetvli zero, a5, e8, m1, ta, ma
398394
; CHECK-NEXT: vslideup.vx v8, v10, a0
399395
; CHECK-NEXT: addi a0, sp, 16
400396
; CHECK-NEXT: vs1r.v v8, (a0)

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