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Hierarchy
Hierarchy extraction is done via Verilog-Perl vhier
.
Visualize with outline-minor-mode
and outshine
.
- For Ubuntu/Debian:
sudo apt-get install libverilog-perl
By default verilog-ext-vhier-current-file
will look at the list of current Verilog open buffers and their corresponding directories to search for modules. In case there is some missing module or an error related with compilation order, you can customize the variable verilog-ext-vhier-command-file
and set a command file that can include a list of the files/includes used for hierarchy extraction, according to vhier
syntax. E.g:
(setq verilog-ext-vhier-command-file "~/my-verilog-project/commands.f")
And being the content of commands.f
:
-y ~/my-verilog-project/some-not-found-dir
~/my-verilog-project/src/my_pkg.sv
+define+SYNTHESIS+0
Customize to provide vhier
a command file where you can add missing
-
vhier-outshine-mode
for hierarchy navigation
Current navigation implementation uses outshine
since it is a very simple method. There are a couple of alternatives to take into consideration to improve current implementation:
-
Using the built-in package hierarchy.el
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As an extension to Treemacs: https://github.com/Alexander-Miller/treemacs/blob/master/Extensions.org