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Typedefs

Gonzalo Larumbe edited this page Feb 20, 2023 · 4 revisions

Background

This feature provides some functions to extract typedefs/classes from a set of files in directories and update variables to improve syntax highlighting and declaration alignment.

By default verilog-pretty-declarations and verilog-pretty-expr will only align built-in types. If you want it to also work on user defined types it is needed to specify which are those types. This feature automates the process of extracting current project typedefs.

To make it efficient it is required to update the value of verilog-align-typedef-regexp with regexp-opt, but doing it frequently (e.g. on file opening, closing or saving) gives a very poor performance. Hence the best approach is to run verilog-ext-typedef-batch-update and update manually the value of verilog-align-typedef-regexp in some other Elisp configuration file.

Usage example

  • Go to project directory, returned by verilog-ext-project-root.

  • Set the variable verilog-ext-align-typedef-uvm-dir to include UVM directories:

     (setq verilog-ext-align-typedef-uvm-dir "/home/user/UVM/1800.2-2020-1.1/src/")
  • M-x verilog-ext-typedef-project-update RET

  • Wait for processing (might take some minutes depending on the number of files)

  • Check if variables were updated:

    • C-h v verilog-ext-align-typedef-words
    • C-h v verilog-ext-align-typedef-words-re
    • C-h v verilog-align-typedef-regexp
  • Update your init file with one of the two following options:

    • Copy the value of verilog-ext-align-typedef-words-re and set it to verilog-align-typedef-regexp

    • Copy the value of verilog-ext-align-typedef-words, remove any undesired word and:

      (setq verilog-align-typedef-regexp
         (eval-when-compile
            (verilog-regexp-words "pasted-value")))
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