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[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (llvm#80945)
To make the structure of TableGen files clear.
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 1 addition & 192 deletions
Original file line numberDiff line numberDiff line change
@@ -1358,189 +1358,6 @@ def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,
13581358
node:$falsev), [{}],
13591359
IntCCtoRISCVCC>;
13601360

1361-
let Predicates = [HasShortForwardBranchOpt], isSelect = 1,
1362-
Constraints = "$dst = $falsev", isCommutable = 1, Size = 8 in {
1363-
// This instruction moves $truev to $dst when the condition is true. It will
1364-
// be expanded to control flow in RISCVExpandPseudoInsts.
1365-
def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst),
1366-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1367-
GPR:$falsev, GPR:$truev),
1368-
[(set GPR:$dst,
1369-
(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
1370-
GPR:$rhs, cond,
1371-
(XLenVT GPR:$truev),
1372-
GPR:$falsev))]>,
1373-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1374-
ReadSFBALU, ReadSFBALU]>;
1375-
}
1376-
1377-
// This should always expand to a branch+c.mv so the size is 6 or 4 if the
1378-
// branch is compressible.
1379-
let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt],
1380-
Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in {
1381-
// This instruction moves $truev to $dst when the condition is true. It will
1382-
// be expanded to control flow in RISCVExpandPseudoInsts.
1383-
// We use GPRNoX0 because c.mv cannot encode X0.
1384-
def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst),
1385-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1386-
GPRNoX0:$falsev, GPRNoX0:$truev),
1387-
[(set GPRNoX0:$dst,
1388-
(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
1389-
(XLenVT GPR:$rhs),
1390-
cond, (XLenVT GPRNoX0:$truev),
1391-
(XLenVT GPRNoX0:$falsev)))]>,
1392-
Sched<[]>;
1393-
}
1394-
1395-
// Conditional binops, that updates update $dst to (op rs1, rs2) when condition
1396-
// is true. Returns $falsev otherwise. Selected by optimizeSelect.
1397-
// TODO: Can we use DefaultOperands on the regular binop to accomplish this more
1398-
// like how ARM does predication?
1399-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8,
1400-
Constraints = "$dst = $falsev" in {
1401-
def PseudoCCADD : Pseudo<(outs GPR:$dst),
1402-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1403-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1404-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1405-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1406-
def PseudoCCSUB : Pseudo<(outs GPR:$dst),
1407-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1408-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1409-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1410-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1411-
def PseudoCCSLL : Pseudo<(outs GPR:$dst),
1412-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1413-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1414-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1415-
ReadSFBALU, ReadSFBALU]>;
1416-
def PseudoCCSRL : Pseudo<(outs GPR:$dst),
1417-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1418-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1419-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1420-
ReadSFBALU, ReadSFBALU]>;
1421-
def PseudoCCSRA : Pseudo<(outs GPR:$dst),
1422-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1423-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1424-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1425-
ReadSFBALU, ReadSFBALU]>;
1426-
def PseudoCCAND : Pseudo<(outs GPR:$dst),
1427-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1428-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1429-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1430-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1431-
def PseudoCCOR : Pseudo<(outs GPR:$dst),
1432-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1433-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1434-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1435-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1436-
def PseudoCCXOR : Pseudo<(outs GPR:$dst),
1437-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1438-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1439-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1440-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1441-
1442-
def PseudoCCADDI : Pseudo<(outs GPR:$dst),
1443-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1444-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1445-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1446-
ReadSFBALU]>;
1447-
def PseudoCCSLLI : Pseudo<(outs GPR:$dst),
1448-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1449-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1450-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1451-
ReadSFBALU]>;
1452-
def PseudoCCSRLI : Pseudo<(outs GPR:$dst),
1453-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1454-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1455-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1456-
ReadSFBALU]>;
1457-
def PseudoCCSRAI : Pseudo<(outs GPR:$dst),
1458-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1459-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1460-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1461-
ReadSFBALU]>;
1462-
def PseudoCCANDI : Pseudo<(outs GPR:$dst),
1463-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1464-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1465-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1466-
ReadSFBALU]>;
1467-
def PseudoCCORI : Pseudo<(outs GPR:$dst),
1468-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1469-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1470-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1471-
ReadSFBALU]>;
1472-
def PseudoCCXORI : Pseudo<(outs GPR:$dst),
1473-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1474-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1475-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1476-
ReadSFBALU]>;
1477-
1478-
// RV64I instructions
1479-
def PseudoCCADDW : Pseudo<(outs GPR:$dst),
1480-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1481-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1482-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1483-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1484-
def PseudoCCSUBW : Pseudo<(outs GPR:$dst),
1485-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1486-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1487-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1488-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1489-
def PseudoCCSLLW : Pseudo<(outs GPR:$dst),
1490-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1491-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1492-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1493-
ReadSFBALU, ReadSFBALU]>;
1494-
def PseudoCCSRLW : Pseudo<(outs GPR:$dst),
1495-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1496-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1497-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1498-
ReadSFBALU, ReadSFBALU]>;
1499-
def PseudoCCSRAW : Pseudo<(outs GPR:$dst),
1500-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1501-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1502-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1503-
ReadSFBALU, ReadSFBALU]>;
1504-
1505-
def PseudoCCADDIW : Pseudo<(outs GPR:$dst),
1506-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1507-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1508-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1509-
ReadSFBALU]>;
1510-
def PseudoCCSLLIW : Pseudo<(outs GPR:$dst),
1511-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1512-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1513-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1514-
ReadSFBALU]>;
1515-
def PseudoCCSRLIW : Pseudo<(outs GPR:$dst),
1516-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1517-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1518-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1519-
ReadSFBALU]>;
1520-
def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
1521-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1522-
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
1523-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
1524-
ReadSFBALU]>;
1525-
1526-
// Zbb/Zbkb instructions
1527-
def PseudoCCANDN : Pseudo<(outs GPR:$dst),
1528-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1529-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1530-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1531-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1532-
def PseudoCCORN : Pseudo<(outs GPR:$dst),
1533-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1534-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1535-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1536-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1537-
def PseudoCCXNOR : Pseudo<(outs GPR:$dst),
1538-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1539-
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1540-
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1541-
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1542-
}
1543-
15441361
multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {
15451362
let usesCustomInserter = 1 in
15461363
def _Using_CC_GPR : Pseudo<(outs valty:$dst),
@@ -2057,15 +1874,6 @@ def : Pat<(binop_allwusers<add> GPR:$rs1, (AddiPair:$rs2)),
20571874
(AddiPairImmSmall AddiPair:$rs2))>;
20581875
}
20591876

2060-
let Predicates = [HasShortForwardBranchOpt] in
2061-
def : Pat<(XLenVT (abs GPR:$rs1)),
2062-
(PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2,
2063-
(XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>;
2064-
let Predicates = [HasShortForwardBranchOpt, IsRV64] in
2065-
def : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32),
2066-
(PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2,
2067-
(i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>;
2068-
20691877
//===----------------------------------------------------------------------===//
20701878
// Experimental RV64 i32 legalization patterns.
20711879
//===----------------------------------------------------------------------===//
@@ -2182,6 +1990,7 @@ include "RISCVInstrInfoZicfiss.td"
21821990
include "RISCVInstrInfoXVentana.td"
21831991
include "RISCVInstrInfoXTHead.td"
21841992
include "RISCVInstrInfoXSf.td"
1993+
include "RISCVInstrInfoSFB.td"
21851994
include "RISCVInstrInfoXCV.td"
21861995

21871996
//===----------------------------------------------------------------------===//

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