Do not apply L0 debugger WA (Disable L3 cache) for highest DG2 steppings

ivvenevt · Compute-Runtime-Automation · commit d9aae805c7a3 · 2022-01-17T13:46:40.000+01:00
Related-To: NEO-6320

Signed-off-by: Igor Venevtsev &lt;igor.venevtsev@intel.com&gt;
diff --git a/level_zero/core/source/debugger/debugger_l0.cpp b/level_zero/core/source/debugger/debugger_l0.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2020-2021 Intel Corporation
+ * Copyright (C) 2020-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -78,7 +78,7 @@ void DebuggerL0::initialize() {
         NEO::MemoryTransferHelper::transferMemoryToAllocation(hwHelper.isBlitCopyRequiredForLocalMemory(hwInfo, *moduleDebugArea),
                                                               *device, moduleDebugArea, 0, &debugArea,
                                                               sizeof(DebugAreaHeader));
-        if (hwHelper.disableL3CacheForDebug()) {
+        if (hwHelper.disableL3CacheForDebug(hwInfo)) {
             device->getGmmHelper()->disableL3CacheForDebug();
         }
     }
diff --git a/opencl/test/unit_test/helpers/hw_helper_tests.cpp b/opencl/test/unit_test/helpers/hw_helper_tests.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2021 Intel Corporation
+ * Copyright (C) 2018-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -1408,13 +1408,13 @@ TEST(HwHelperTests, whenBlitterSupportIsDisabledThenDontExposeAnyBcsEngine) {
 using NotATSOrDG2 = AreNotGfxCores<IGFX_XE_HP_CORE, IGFX_XE_HPG_CORE>;
 HWTEST2_F(HwHelperTest, givenNotAtsOrDg2WhenDisableL3ForDebugCalledThenFalseIsReturned, NotATSOrDG2) {
     const auto &hwHelper = HwHelper::get(renderCoreFamily);
-    EXPECT_FALSE(hwHelper.disableL3CacheForDebug());
+    EXPECT_FALSE(hwHelper.disableL3CacheForDebug(*defaultHwInfo));
 }
 
 using ATSOrDG2 = IsWithinGfxCore<IGFX_XE_HP_CORE, IGFX_XE_HPG_CORE>;
 HWTEST2_F(HwHelperTest, givenAtsOrDg2WhenDisableL3ForDebugCalledThenTrueIsReturned, ATSOrDG2) {
     const auto &hwHelper = HwHelper::get(renderCoreFamily);
-    EXPECT_TRUE(hwHelper.disableL3CacheForDebug());
+    EXPECT_TRUE(hwHelper.disableL3CacheForDebug(*defaultHwInfo));
 }
 
 HWTEST_F(HwHelperTest, givenHwHelperWhenGettingIfRevisionSpecificBinaryBuiltinIsRequiredThenFalseIsReturned) {
@@ -1448,4 +1448,4 @@ HWTEST2_F(HwHelperTest, givenHwInfoConfigWhenCheckingForceNonGpuCoherencyWAThenF
     const auto &hwHelper = HwHelper::get(renderCoreFamily);
     EXPECT_FALSE(hwHelper.forceNonGpuCoherencyWA(true));
     EXPECT_FALSE(hwHelper.forceNonGpuCoherencyWA(false));
-}
+}
diff --git a/opencl/test/unit_test/xe_hpg_core/dg2/hw_helper_tests_dg2.cpp b/opencl/test/unit_test/xe_hpg_core/dg2/hw_helper_tests_dg2.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2021-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -74,6 +74,28 @@ DG2TEST_F(HwHelperTestsDg2, givenRevisionEnumAndPlatformFamilyTypeThenProperValu
     }
 }
 
+DG2TEST_F(HwHelperTestsDg2, givenRevisionEnumAndDisableL3CacheForDebugCalledThenCorrectValueIsReturned) {
+    uint32_t steppings[] = {
+        REVISION_A0,
+        REVISION_A1,
+        REVISION_B,
+        REVISION_C,
+        CommonConstants::invalidStepping,
+    };
+
+    const auto &hwHelper = HwHelper::get(hardwareInfo.platform.eRenderCoreFamily);
+    const auto &hwInfoConfig = *HwInfoConfig::get(hardwareInfo.platform.eProductFamily);
+
+    for (auto stepping : steppings) {
+        hardwareInfo.platform.usRevId = hwInfoConfig.getHwRevIdFromStepping(stepping, hardwareInfo);
+        if (stepping < REVISION_B) {
+            EXPECT_TRUE(hwHelper.disableL3CacheForDebug(hardwareInfo));
+        } else {
+            EXPECT_FALSE(hwHelper.disableL3CacheForDebug(hardwareInfo));
+        }
+    }
+}
+
 DG2TEST_F(HwHelperTestsDg2, givenDg2WhenSetForceNonCoherentThenProperFlagSet) {
     using FORCE_NON_COHERENT = typename FamilyType::STATE_COMPUTE_MODE::FORCE_NON_COHERENT;
 
@@ -127,4 +149,4 @@ DG2TEST_F(HwHelperTestsDg2, givenNotEnabledSliceWhenComputeUnitsUsedForScratchTh
     auto &hwHelper = HwHelper::get(hwInfo.platform.eRenderCoreFamily);
 
     EXPECT_THROW(hwHelper.getComputeUnitsUsedForScratch(&hwInfo), std::exception);
-}
+}
diff --git a/shared/source/device/device.cpp b/shared/source/device/device.cpp
@@ -219,7 +219,7 @@ bool Device::createDeviceImpl() {
     }
 
     auto &hwHelper = HwHelper::get(hwInfo.platform.eRenderCoreFamily);
-    if (getDebugger() && hwHelper.disableL3CacheForDebug()) {
+    if (getDebugger() && hwHelper.disableL3CacheForDebug(hwInfo)) {
         getGmmHelper()->disableL3CacheForDebug();
     }
 
diff --git a/shared/source/helpers/hw_helper.h b/shared/source/helpers/hw_helper.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2021 Intel Corporation
+ * Copyright (C) 2018-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -151,7 +151,7 @@ class HwHelper {
     virtual uint64_t getMaxMemAllocSize() const = 0;
     virtual bool isStatelesToStatefullWithOffsetSupported() const = 0;
     virtual void encodeBufferSurfaceState(EncodeSurfaceStateArgs &args) = 0;
-    virtual bool disableL3CacheForDebug() const = 0;
+    virtual bool disableL3CacheForDebug(const HardwareInfo &hwInfo) const = 0;
     virtual bool isRevisionSpecificBinaryBuiltinRequired() const = 0;
     virtual bool forceNonGpuCoherencyWA(bool requiresCoherency) const = 0;
 
@@ -387,7 +387,7 @@ class HwHelperHw : public HwHelper {
     uint64_t getMaxMemAllocSize() const override;
     bool isStatelesToStatefullWithOffsetSupported() const override;
     void encodeBufferSurfaceState(EncodeSurfaceStateArgs &args) override;
-    bool disableL3CacheForDebug() const override;
+    bool disableL3CacheForDebug(const HardwareInfo &hwInfo) const override;
     bool isRevisionSpecificBinaryBuiltinRequired() const override;
     bool forceNonGpuCoherencyWA(bool requiresCoherency) const override;
 
diff --git a/shared/source/helpers/hw_helper_base.inl b/shared/source/helpers/hw_helper_base.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2019-2021 Intel Corporation
+ * Copyright (C) 2019-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -702,7 +702,7 @@ void HwHelperHw<GfxFamily>::encodeBufferSurfaceState(EncodeSurfaceStateArgs &arg
 }
 
 template <typename GfxFamily>
-bool HwHelperHw<GfxFamily>::disableL3CacheForDebug() const {
+bool HwHelperHw<GfxFamily>::disableL3CacheForDebug(const HardwareInfo &) const {
     return false;
 }
 template <typename GfxFamily>
diff --git a/shared/source/xe_hp_core/hw_helper_xe_hp_core.cpp b/shared/source/xe_hp_core/hw_helper_xe_hp_core.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2021-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -155,7 +155,7 @@ uint32_t HwHelperHw<Family>::getDefaultRevisionId(const HardwareInfo &hwInfo) co
 }
 
 template <>
-bool HwHelperHw<Family>::disableL3CacheForDebug() const {
+bool HwHelperHw<Family>::disableL3CacheForDebug(const HardwareInfo &) const {
     return true;
 }
 
diff --git a/shared/source/xe_hpg_core/hw_helper_xe_hpg_core.cpp b/shared/source/xe_hpg_core/hw_helper_xe_hpg_core.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021 Intel Corporation
+ * Copyright (C) 2021-2022 Intel Corporation
  *
  * SPDX-License-Identifier: MIT
  *
@@ -114,8 +114,8 @@ uint32_t HwHelperHw<Family>::computeSlmValues(const HardwareInfo &hwInfo, uint32
 }
 
 template <>
-bool HwHelperHw<Family>::disableL3CacheForDebug() const {
-    return true;
+bool HwHelperHw<Family>::disableL3CacheForDebug(const HardwareInfo &hwInfo) const {
+    return isWorkaroundRequired(REVISION_A0, REVISION_B, hwInfo);
 }
 
 template class HwHelperHw<Family>;

Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`	`1`	`/*`
`2`		`- * Copyright (C) 2020-2021 Intel Corporation`
	`2`	`+ * Copyright (C) 2020-2022 Intel Corporation`
`3`	`3`	`*`
`4`	`4`	`* SPDX-License-Identifier: MIT`
`5`	`5`	`*`
`@@ -78,7 +78,7 @@ void DebuggerL0::initialize() {`
`78`	`78`	`NEO::MemoryTransferHelper::transferMemoryToAllocation(hwHelper.isBlitCopyRequiredForLocalMemory(hwInfo, *moduleDebugArea),`
`79`	`79`	`*device, moduleDebugArea, 0, &debugArea,`
`80`	`80`	`sizeof(DebugAreaHeader));`
`81`		`- if (hwHelper.disableL3CacheForDebug()) {`
	`81`	`+ if (hwHelper.disableL3CacheForDebug(hwInfo)) {`
`82`	`82`	`device->getGmmHelper()->disableL3CacheForDebug();`
`83`	`83`	`}`
`84`	`84`	`}`
Original file line number	Diff line number	Diff line change
`@@ -219,7 +219,7 @@ bool Device::createDeviceImpl() {`
`219`	`219`	`}`
`220`	`220`
`221`	`221`	`auto &hwHelper = HwHelper::get(hwInfo.platform.eRenderCoreFamily);`
`222`		`- if (getDebugger() && hwHelper.disableL3CacheForDebug()) {`
	`222`	`+ if (getDebugger() && hwHelper.disableL3CacheForDebug(hwInfo)) {`
`223`	`223`	`getGmmHelper()->disableL3CacheForDebug();`
`224`	`224`	`}`
`225`	`225`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`	`1`	`/*`
`2`		`- * Copyright (C) 2019-2021 Intel Corporation`
	`2`	`+ * Copyright (C) 2019-2022 Intel Corporation`
`3`	`3`	`*`
`4`	`4`	`* SPDX-License-Identifier: MIT`
`5`	`5`	`*`
`@@ -702,7 +702,7 @@ void HwHelperHw<GfxFamily>::encodeBufferSurfaceState(EncodeSurfaceStateArgs &arg`
`702`	`702`	`}`
`703`	`703`
`704`	`704`	`template <typename GfxFamily>`
`705`		`-bool HwHelperHw<GfxFamily>::disableL3CacheForDebug() const {`
	`705`	`+bool HwHelperHw<GfxFamily>::disableL3CacheForDebug(const HardwareInfo &) const {`
`706`	`706`	`return false;`
`707`	`707`	`}`
`708`	`708`	`template <typename GfxFamily>`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`	`1`	`/*`
`2`		`- * Copyright (C) 2021 Intel Corporation`
	`2`	`+ * Copyright (C) 2021-2022 Intel Corporation`
`3`	`3`	`*`
`4`	`4`	`* SPDX-License-Identifier: MIT`
`5`	`5`	`*`
`@@ -155,7 +155,7 @@ uint32_t HwHelperHw<Family>::getDefaultRevisionId(const HardwareInfo &hwInfo) co`
`155`	`155`	`}`
`156`	`156`
`157`	`157`	`template <>`
`158`		`-bool HwHelperHw<Family>::disableL3CacheForDebug() const {`
	`158`	`+bool HwHelperHw<Family>::disableL3CacheForDebug(const HardwareInfo &) const {`
`159`	`159`	`return true;`
`160`	`160`	`}`
`161`	`161`