Support null register to be used in general register category

In some cases we need to emit `%null` vISA register as an operand for
a vISA instruction consuming the vector operand. Before the change,
only raw operand could be used as a null operand.

Author: vmustya

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

@@ -508,17 +508,17 @@ class GenXKernelBuilder {
   VISA_VectorOpnd *createDestination(Value *Dest,
                                      genx::Signedness Signed,
                                      unsigned *Offset = nullptr);
-  VISA_VectorOpnd *createSourceOperand(Instruction *Inst,
-                                       genx::Signedness Signed,
-                                       unsigned OperandNum, genx::BaleInfo BI,
-                                       unsigned Mod = 0,
-                                       genx::Signedness *SignedRes = nullptr,
-                                       unsigned MaxWidth = 16);
+  VISA_VectorOpnd *
+  createSourceOperand(Instruction *Inst, genx::Signedness Signed,
+                      unsigned OperandNum, genx::BaleInfo BI, unsigned Mod = 0,
+                      genx::Signedness *SignedRes = nullptr,
+                      unsigned MaxWidth = 16, bool IsNullAllowed = false);
   VISA_VectorOpnd *createSource(Value *V, genx::Signedness Signed, bool Baled,
                                 unsigned Mod = 0,
                                 genx::Signedness *SignedRes = nullptr,
                                 unsigned MaxWidth = 16,
-                                unsigned *Offset = nullptr, bool IsBF = false);
+                                unsigned *Offset = nullptr, bool IsBF = false,
+                                bool IsNullAllowed = false);
   VISA_VectorOpnd *createSource(Value *V, genx::Signedness Signed,
                                 unsigned MaxWidth = 16,
                                 unsigned *Offset = nullptr);
@@ -1718,15 +1718,17 @@ GenXKernelBuilder::createDestination(Value *Dest, genx::Signedness Signed,
   }
 }
 
-VISA_VectorOpnd *GenXKernelBuilder::createSourceOperand(
-    Instruction *Inst, Signedness Signed, unsigned OperandNum,
-    genx::BaleInfo BI, unsigned Mod, Signedness *SignedRes, unsigned MaxWidth) {
+VISA_VectorOpnd *
+GenXKernelBuilder::createSourceOperand(Instruction *Inst, Signedness Signed,
+                                       unsigned OperandNum, genx::BaleInfo BI,
+                                       unsigned Mod, Signedness *SignedRes,
+                                       unsigned MaxWidth, bool IsNullAllowed) {
   Value *V = Inst->getOperand(OperandNum);
   auto IID = vc::InternalIntrinsic::getInternalIntrinsicID(Inst);
   bool IsBF = IID == vc::InternalIntrinsic::cast_from_bf16;
 
   return createSource(V, Signed, BI.isOperandBaled(OperandNum), Mod, SignedRes,
-                      MaxWidth, nullptr, IsBF);
+                      MaxWidth, nullptr, IsBF, IsNullAllowed);
 }
 
 VISA_PredOpnd *
@@ -2000,14 +2002,29 @@ VISA_VectorOpnd *GenXKernelBuilder::createSource(Value *V, Signedness Signed,
                                                  bool Baled, unsigned Mod,
                                                  Signedness *SignedRes,
                                                  unsigned MaxWidth,
-                                                 unsigned *Offset, bool IsBF) {
+                                                 unsigned *Offset, bool IsBF,
+                                                 bool IsNullAllowed) {
   LLVM_DEBUG(dbgs() << "createSource for " << (Baled ? "baled" : "non-baled")
                     << (IsBF ? " brain" : " non-brain") << " value: ");
   LLVM_DEBUG(V->dump());
   LLVM_DEBUG(dbgs() << "\n");
   if (SignedRes)
     *SignedRes = Signed;
-  if (auto C = dyn_cast<Constant>(V)) {
+  // Null register is required
+  if (IsNullAllowed && isa<UndefValue>(V)) {
+    Region R(V);
+    if (Offset)
+      R.Offset = *Offset;
+    if (R.NumElements == 1)
+      R.VStride = R.Stride = 0;
+
+    VISA_GenVar *NullDecl = nullptr;
+    CISA_CALL(Kernel->GetPredefinedVar(NullDecl, PREDEFINED_NULL));
+
+    return createRegionOperand(&R, NullDecl, Signed, Mod, false /*IsDst*/,
+                               MaxWidth);
+  }
+  if (auto *C = dyn_cast<Constant>(V)) {
     if (Mod) {
       // Need to negate constant.
       IGC_ASSERT_MESSAGE(Mod == MODIFIER_NEG, "unexpected modifier");
@@ -3387,8 +3404,9 @@ void GenXKernelBuilder::buildIntrinsic(CallInst *CI, unsigned IntrinID,
         MaxWidth =
             cast<IGCLLVM::FixedVectorType>(CI->getType())->getNumElements();
       }
-      ResultOperand = createSourceOperand(CI, Signed, AI.getArgIdx(), BI, 0,
-                                          nullptr, MaxWidth);
+      ResultOperand =
+          createSourceOperand(CI, Signed, AI.getArgIdx(), BI, 0, nullptr,
+                              MaxWidth, AI.generalNullAllowed());
     }
     return ResultOperand;
   };

IGC/VectorCompiler/lib/GenXCodeGen/GenXConstants.cpp

@@ -531,16 +531,14 @@ bool ConstantLoadHelper::visitCallInst(CallInst &CI) {
       // Allow constant if intrinsic descriptor allows it for this arg.
       if (AI.getCategory() == GenXIntrinsicInfo::CACHEOPTS)
         continue;
+      // Allow constant, if it's undefined, and null register is allowed.
+      if (isa<UndefValue>(C) && AI.isNullAllowed())
+        continue;
       // If it is a RAW operand, allow the constant if it's in the trailing
-      // null region (it must be a null constant if so), or if the value
-      // is undefined and RAW_NULLALLOWED is enabled.
-      if (AI.isRaw()) {
-        if ((unsigned)AI.getArgIdx() >= MaxRawOperands) {
-          IGC_ASSERT(C->isNullValue());
-          continue;
-        }
-        if (isa<UndefValue>(C) && AI.rawNullAllowed())
-          continue;
+      // null region (it must be a null constant if so).
+      if (AI.isRaw() && (unsigned)AI.getArgIdx() >= MaxRawOperands) {
+        IGC_ASSERT(C->isNullValue());
+        continue;
       }
       // Also allow constant if it is undef in a TWOADDR
       if (isa<UndefValue>(C) && AI.getCategory() == GenXIntrinsicInfo::TWOADDR)

IGC/VectorCompiler/lib/GenXCodeGen/GenXIntrinsics.h

@@ -53,7 +53,7 @@ class GenXIntrinsicInfo {
     // currently the maximum needed is 5.
     //
     // At the moment, the GENERAL category has 4 unused flag bits available
-    // to it, the RAW category has 13 unused bits, and the ARGCOUNT category
+    // to it, the RAW category has 11 unused bits, and the ARGCOUNT category
     // has 13 unused bits. No other categories make use of the flags yet,
     // so it should be a good while yet before it's necessary to resize
     // the bitfields.
@@ -172,6 +172,7 @@ class GenXIntrinsicInfo {
     MODIFIER_EXTONLY =      GENX_ITR_FLAGENUM(8, 3), // src modifier: extend only
     DIRECTONLY =            GENX_ITR_FLAGVAL(10), // indirect region not allowed
     IMM16ONLY =             GENX_ITR_FLAGVAL(11), // source allowed to be only 16 bit immediate
+    NULLALLOWED =           GENX_ITR_FLAGVAL(12), // source allowed to be null register
 
   };
   struct ArgInfo {
@@ -217,6 +218,17 @@ class GenXIntrinsicInfo {
       IGC_ASSERT(isRaw());
       return Info & RAW_NULLALLOWED;
     }
+    bool generalNullAllowed() const {
+      IGC_ASSERT(isGeneral());
+      return Info & NULLALLOWED;
+    }
+    bool isNullAllowed() const {
+      if (isGeneral())
+        return generalNullAllowed();
+      if (isRaw())
+        return rawNullAllowed();
+      return false;
+    }
     // isArgOrRet : test whether this field has an arg index
     bool isArgOrRet() const {
       if (isGeneral()) return true;