Force declared variables to physical registers through

compiler options

Force declared variables to physical registers through compiler options

Author: houjenko

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -4432,6 +4432,11 @@ namespace IGC
             SaveOption(vISA_ShaderDumpFilter, regex);
         }
 
+        if (auto *str = IGC_GET_REGKEYSTRING(ForceAssignRhysicalReg))
+        {
+            SaveOption(vISA_ForceAssignRhysicalReg, str);
+        }
+
         // In Vulkan and OGL buffer variable memory reads and writes within
         // a single shader invocation must be processed in order.
         if (m_program->m_DriverInfo->DisableDpSendReordering())

IGC/common/igc_flags.h

@@ -353,6 +353,7 @@ DECLARE_IGC_REGKEY(bool, AddExtraIntfInfo,                false, "Will add extra
 DECLARE_IGC_REGKEY(bool, SimdEarlyOut_9,                false, "Force compiler simd early out for dx9", true)
 
 DECLARE_IGC_GROUP("Debugging features")
+DECLARE_IGC_REGKEY(debugString, ForceAssignRhysicalReg,     0, "Force assigning dclId to phyiscal reg.", true)
 DECLARE_IGC_REGKEY(bool, InitializeUndefValueEnable,    false, "Setting this to 1/true initializes all undefs in URB payload to 0", false)
 DECLARE_IGC_REGKEY(bool, InitializeRegistersEnable,     false, "Setting this to 1/true initializes all GRFs, Flag and address registers to 0 at the beginning of the shader", false)
 DECLARE_IGC_REGKEY(bool, InitializeAddressRegistersBeforeUse,     false, "Setting this to 1 (true) initializes address register to 0 before each use", false)

visa/BuildCISAIRImpl.cpp

@@ -1643,7 +1643,40 @@ int CISA_IR_Builder::Compile(const char* nameInput, std::ostream* os, bool emit_
                     m_options.getuInt32Option(vISA_Linker));
         }
     }
+    const char* rawStr = m_options.getOptionCstr(vISA_ForceAssignRhysicalReg);
+    if (rawStr && *rawStr != '\0')
+    {
+        std::vector<int> token;
+        std::map<int, int> forceAssign;
+        const char* DELIMITERS = ":, ";
+        std::string line(rawStr);
+        std::size_t pos = 0;
+        std::size_t found;
+        for (; (found = line.find_first_of(DELIMITERS, pos)) != std::string::npos; ++pos) {
+            // Skip consecutive whitespaces.
+            if (found == pos)
+                continue;
+            token.push_back(std::stoi(line.substr(pos, found - pos)));
+            pos = found;
+        }
+        if (pos < line.length())
+            token.push_back(std::stoi(line.substr(pos)));
+
+        for (unsigned int i = 0; i < token.size() - 1; i += 2)
+        {
+            forceAssign[token[i]] = token[i+1];
+        }
 
+        for (G4_Declare* dcl : m_kernelsAndFunctions.front()->getKernel()->Declares)
+        {
+            if (forceAssign.find(dcl->getDeclId()) != forceAssign.end())
+            {
+                std::cerr << "Force assigning DeclId : " << dcl->getDeclId() << " to r" << forceAssign[dcl->getDeclId()] << "\n";
+                dcl->getRegVar()->setPhyReg(m_kernelsAndFunctions.front()->getIRBuilder()->phyregpool.getGreg(forceAssign[dcl->getDeclId()]), 0);
+                dcl->dump();
+            }
+        }
+     }
 
 
     VISAKernelImpl* oldMainKernel = nullptr;

visa/include/VISAOptionsDefs.h

@@ -52,6 +52,7 @@ DEF_VISA_OPTION(vISA_removeInstrinsics,     ET_BOOL, "-removeInstrinsics",     U
 DEF_VISA_OPTION(vISA_addSWSBInfo,           ET_BOOL, "-addSWSBInfo",     UNUSED, true)
 DEF_VISA_OPTION(vISA_DumpRAIntfGraph,       ET_BOOL, "-dumpintf",        UNUSED, false)
 DEF_VISA_OPTION(vISA_DumpGenOffset,         ET_BOOL, "-dumpgenoffset",   UNUSED, false)
+DEF_VISA_OPTION(vISA_ForceAssignRhysicalReg,ET_CSTR, "-forceAssignRhysicalReg", UNUSED, NULL)
 
 //=== Optimization options ===
 DEF_VISA_OPTION(vISA_EnableAlways,          ET_BOOL, NULLSTR,            UNUSED, true)