Allow alignment improvement for all cases except stateful accesses, in which

the base of stateful surface could be as little as DW, thus we can assume align 4
on stateful messages.

Change-Id: Id264f87dff73da7c73d31cd4ba7bed64711f17f8

Author: jgu222

IGC/Compiler/CISACodeGen/VectorPreProcess.cpp

@@ -598,6 +598,21 @@ bool VectorPreProcess::splitStore(
     if (IGC_IS_FLAG_ENABLED(EnableSplitUnalignedVector))
     {
         // byte and word-aligned stores can only store a dword at a time.
+        unsigned int alignment = ASI.getAlignment();
+        if (isStoreInst && alignment < 4)
+        {
+            uint32_t newAlign = getKnownAlignment(ASI.getPointerOperand(), *m_DL);
+            if (newAlign > alignment)
+            {
+                // For the same reason as Load, use DW-aligned for OCL stateful.
+                StoreInst* aSI = dyn_cast<StoreInst>(SI);
+                if (aSI && newAlign > 4 && isStatefulAddrSpace(aSI->getPointerAddressSpace()))
+                {
+                    newAlign = 4;
+                }
+                ASI.setAlignment(newAlign);
+            }
+        }
         bool needsDWordSplit =
             (!isStoreInst ||
                 m_CGCtx->m_DriverInfo.splitUnalignedVectors() ||
@@ -753,6 +768,28 @@ bool VectorPreProcess::splitLoad(
     if (IGC_IS_FLAG_ENABLED(EnableSplitUnalignedVector))
     {
         // byte and word-aligned loads can only load a dword at a time.
+        unsigned int alignment = ALI.getAlignment();
+        if (!isLdRaw && alignment < 4)
+        {
+            uint32_t newAlign = getKnownAlignment(ALI.getPointerOperand(), *m_DL);
+            if (newAlign > alignment)
+            {
+                //  For OCL stateful, the base can be as little as DW-aligned. To be safe,
+                //  need to use DW-aligned. For example,
+                //       % 0 = add i32 0, 16
+                //       % 4 = inttoptr i32 % 0 to <8 x i16> addrspace(131073) *
+                //       %5 = load <8 x i16>, <8 x i16> addrspace(131073) * %4, align 2
+                //  newAlign from getKnownAlignment() is 16. But we can only set align to 4 as
+                //  the base of this stateful could be just DW-aligned.
+                LoadInst* aLI = dyn_cast<LoadInst>(LI);
+                if (aLI && newAlign > 4 && isStatefulAddrSpace(aLI->getPointerAddressSpace()))
+                {
+                    newAlign = 4;
+                }
+                ALI.setAlignment(newAlign);
+            }
+        }
+
         if ((isLdRaw || !WI.isUniform(ALI.getInst())) && ALI.getAlignment() < 4)
             splitSize = 4;
     }
@@ -1540,4 +1577,4 @@ bool VectorPreProcess::runOnFunction(Function& F)
         m_WorkList.clear();
     }
     return changed;
-}
+}

IGC/Compiler/CISACodeGen/helper.cpp

@@ -100,6 +100,14 @@ namespace IGC
         return temp.u32Val;
     }
 
+    // Return true if AS is for a stateful surface.
+    //    Stateful surface should have an encoded AS that is bigger than
+    //    ADDRESS_SPACE_NUM_ADDRESSES.
+    bool isStatefulAddrSpace(unsigned AS)
+    {
+        return AS > ADDRESS_SPACE_NUM_ADDRESSES;
+    }
+
     bool isDummyBasicBlock(llvm::BasicBlock* BB)
     {
         if (BB->size() != 1)

IGC/Compiler/CISACodeGen/helper.h

@@ -183,6 +183,7 @@ namespace IGC
         unsigned uniqueIndAS);
 
     unsigned SetBufferAsBindless(unsigned addressSpaceOfPtr, BufferType bufferType);
+    bool isStatefulAddrSpace(unsigned AS);
 
     BufferType DecodeAS4GFXResource(unsigned addrSpace, bool& directIdx, unsigned& bufId);
     int getConstantBufferLoadOffset(llvm::LoadInst* ld);